Intel D2500CC Specification page 79

Table 45. Port 80h POST Codes (continued)
Port 80 Code
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x58
0x59
0x5A
0x5B
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
Progress Code Enumeration
CPU DXE Phase
CPU DXE Phase begin
Refresh memory space attributes according to MTRRs
Load the microcode if needed
Initialize strings to HII database
Initialize MP support
CPU DXE Phase End
CPU DXE SMM Phase
CPU DXE SMM Phase begin
Relocate SM bases for all APs
CPU DXE SMM Phase end
Enumerating PCI buses
Allocating resources to PCI bus
Hot Plug PCI controller initialization
Resetting USB bus
Reserved for USB
ATA/ATAPI/SATA
Resetting PATA/SATA bus and all devices
Reserved for ATA
BDS driver entry point initialize
BDS service routine entry point (can be called multiple times)
BDS Step2
BDS Step3
BDS Step4
BDS Step5
BDS Step6
BDS Step7
BDS Step8
BDS Step9
BDS Step10
BDS Step11
BDS Step12
BDS Step13
BDS Step14
BDS return to DXE core (should not get here)
Board Status and Error Messages
I/O BUSES
USB
BDS
continued
79