Sata Support; Real-Time Clock Subsystem - Intel D2500CC Specification

Technical product specification for intel desktop board d2500cc
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For information about
The location of the USB connectors on the back panel
The location of the front panel USB headers
1.5.3

SATA Support

The board provides two SATA interface connectors that support one device per
connector.
The board's SATA controller offers independent SATA ports with a theoretical
maximum transfer rate of 3.0 Gb/s on each port. One device can be installed on each
port for a maximum of two SATA devices. A point-to-point interface is used for host to
device connections, unlike PATA which supports a master/slave configuration and two
devices on each channel.
For compatibility, the underlying SATA functionality is transparent to the operating
system. The SATA controller supports IDE and AHCI configuration and can operate in
both legacy and native modes. In legacy mode, standard ATA I/O and IRQ resources
are assigned (IRQ 14 and 15). In native mode, standard Conventional PCI bus
resource steering is used. Native mode is the preferred mode for configurations using
the Windows Vista* operating system.
For information about
Obtaining AHCI driver
The location of the SATA connectors
1.6

Real-Time Clock Subsystem

A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the
computer is not plugged into a wall socket, the battery has an estimated life of three
years. When the computer is plugged in, the standby current from the power supply
extends the life of the battery. The clock is accurate to ± 13 minutes/year at 25 ºC
with 3.3 VSB applied.
NOTE
If the battery and AC power fail, custom defaults, if previously saved, will be loaded
into CMOS RAM at power-on.
When the voltage drops below a certain level, the BIOS Setup program settings stored
in CMOS RAM (for example, the date and time) might not be accurate. Replace the
battery with an equivalent one. Figure 1 on page 13 shows the location of the battery.
Product Description
Refer to
Figure 9, page 41
Figure 11, page 43
Refer to
Section 1.2, page 16
Figure 11, page 43
23

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