Canon CANOSCAN FB330 series Service Manual page 60

CHAPTER 2
D. Scanning Unit Drive Motor Control Circuit
Figure 2-21 shows a block diagram of the scanning unit drive motor control circuit. The
CPU analyzes each command sent from the host computer via gate array and sets to generate
Pulse Motor Forward Clock (PMFCK) based on the scaling for the gate array. The gate array
converts the PMFCK signals into the four phase motor drive pulse signals (PHAP, PHAN, PHBP,
PHBN), which are sent to the scanning unit drive motor via the motor driver.
When the host computer changes the resolution, the CPU sets to change the frequency of
the PMFCK signals for the gate array, then changes the rotating speed of the scanning unit
drive motor.
To host
computer
2 - 32
COPYRIGHT © 1999 CANON INC. CANOSCAN FB330/FB630 SERIES REV.0 OCT. 1999 PRINTED IN JAPAN (IMPRIME AU JAPON)
Main PCB
CPU
PMENB PMFCK
PHAP
PHAN
Gate array
PHBP
PHBN
Figure 2-21
Scanning unit
drive motor
AP J3-17
AN -18
Motor
M1
BP -19
driver
BN -20