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Part 2: Product Specifications
Reverse Req [Input]
This signal goes Low when the recovery process (data re-transmission) is taking
place during data transmission from the host computer to the printer.
In response to a Low Ack Reverse signal, Reverse Req signal goes High.
When switching from the idle state of the forward data transmission phase to the
reverse data transmission phase, i.e. data is transferred from the printer to the host
computer, this signal goes Low.
The Low period indicates it is in the reverse data transmission phase.
When the reverse data transmission phase is switched to the forward data
transmission phase, this signal goes High.
Periph Req [Output]
If the printer requests reverse data transmission during the forward data
transmission, this signal goes Low. When the host computer switches over from the
forward data transmission phase to the reverse data transmission phase, together
with the Ack Reverse signal, the Periph Req signal goes High in response to the host
computer's Low Reverse Request signal.
1284 Active [Input]
During the negotiation phase, this signal goes High and remains High during ECP
mode to indicate bidirectional operation.
After ending ECP mode, this signal goes Low and enters the termination phase.
9) Timing
Compatible Mode
The parallel interface for compatible mode transfers data in 8-bit units. Data is
transferred with the STROBE, BUSY, and ACKNLG handshake signals.
When the printer receives the data (Data 1-8) and STROBE signal from the host
computer and the STROBE signal is Low, the printer controller (which controls the
parallel interface) outputs the BUSY signal and latches the data. After the BUSY
signal is output, the printer controller sends the latched data from the DRAM bus to
the receive buffer in the DRAM. After the data is completely written into the receive
buffer in the DRAM, the printer controller outputs the ACKNLG signal and sets the
BUSY signal to "Low." Then it waits for the next data input from the host computer.
0.5ms
1.0ms
Min.
Min.
DATA 1 to 8
STROBE
BUSY
ACKNLG
Figure 2-10 Timing Chart (Compatible Mode)
0.5ms
Min.
Approx.
2-18
BJC-2000
BJC-2000
6ms
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