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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
7.10
General AC and DC Characteristics
Table 12. General AC and DC Characteristics
Symbol
Parameter Description
V
Input High Voltage
IH
V
Input Low Voltage
IL
V
Output High Voltage
OH
V
Output Low Voltage
OL
I
Tristate Leakage Pullup
LEAK_P
I
Tristate Leakage Pulldown
LEAK_N
I
Output High Current
OH
I
Output Low Current
OL
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal V
3. I
and I
are measured at V
OL
OH
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the "Power-Up Timing Requirements" chapter for more
information.
32
Table 12 shows the AMD Sempron processor model 10 AC and
DC characteristics of the Southbridge, JTAG, test, and
miscellaneous pins.
Condition
V
IN
(Ground)
V
= V
IN
Nominal
. Scale parameters between V
CC_CORE
maximum and V
minimum, respectively.
OL
OH
Electrical Data
Min
(V
/ 2) +
CC_CORE
200 mV
–300
V
–
CC_CORE
400
–300
= VSS
–1
CC_CORE
6
minimum and V
CC_CORE.
31994A —1 August 2004
Max
Units Notes
V
+
CC_CORE
V
300 mV
350
mV
V
+
CC_CORE
mV
300
400
mV
mA
µA
600
–6
mA
mA
maximum.
CC_CORE.
Chapter 7
1, 2
1, 2
3
3
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