Pci Interrupt Routing Map - Intel D845GLLY Using Manual

Technical Product Specification for Intel Desktop Boards using the Intel 845GL Chipset
Table 19.

PCI Interrupt Routing Map

PCI Interrupt Source
ICH4 USB UHCI controller 1 INTA
SMBus controller
ICH4 USB UHCI controller 2
AC '97 ICH4 Audio/Modem
ICH4 LAN
ICH4 USB UHCI controller 3
ICH4 USB 2.0 EHCI controller
PCI bus connector 1
PCI bus connector 2
PCI bus connector 3
PCI bus connector 4
✏
NOTE
In PIC mode, the ICH4 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6,
7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a
unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or
more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 18 for the
allocation of PIRQ lines to IRQ signals in APIC mode.
42
ICH4 PIRQ Signal Name
PIRQA PIRQB PIRQC
INTB
INTB
INTC
INTD INTC INTA
INTB
PIRQD PIRQE PIRQF
INTB
INTA
INTD INTA
INTC INTB
INTB
INTA INTC
PIRQG PIRQH
INTD
INTB INTC
INTA INTD
INTD