Input/Output Address Map - IBM NetVista X40 Technical Information Manual

Input/output address map

Table 33. I/O address map
Address (hex)
0000–000F
0010–001F
0020–0021
0023–003F
0040–0043
0044–00FF
0060
0061
0064
0070, bit 7
0070, bits 6:0
0071
0072–007F
0080
008F
0080–008F
0090–0091
0092
0093–009F
00A0–00A1
00A2–00BF
00C0–00DF
00E0–00EF
00F0
00F1–016F
0170–0177
01F0–01F7
0200–0207
0220–0227
0228–0277
0278–027F
34
Technical Information
The following lists resource assignments for the I/O address map. Any addresses that
are not shown are reserved.
Size
16 bytes
16 bytes
2 bytes
30 bytes
4 bytes
28 bytes
1 byte
1 byte
1 byte
1 bit
1 bit
1 byte
14 bytes
1 byte
1 byte
16 bytes
15 bytes
1 byte
15 bytes
2 bytes
30 bytes
31 bytes
16 bytes
1 byte
127 bytes
8 bytes
8 bytes
8 bytes
8 bytes
80 bytes
8 bytes
Description
DMA 1
General I/O locations - available to PCI bus
Interrupt controller 1
General I/O locations - available to PCI bus
Counter/timer 1
General I/O locations - available to PCI bus
Keyboard controller byte - reset IRQ
System port B
Keyboard controller, CMB/STAT byte
Enable NMI
Real-time clock, address
Real-time clock, data
General I/O locations - available to PCI bus
POST checkpoint register during POST only
Refresh page register
ICH1, DMA page registers
General I/O locations - available to PCI bus
PS/2 keyboard controller registers
General I/O locations
Interrupt controller 2
APM control
DMA 2
General I/O locations - available to PCI bus
Coprocessor error register
General I/O locations - available to PCI bus
Secondary IDE channel
Primary IDE channel
Available
Serial port 3 or 4
General I/O locations - available to PCI bus
Available