L2 Cache; Chip Set Control; System Memory - IBM NetVista X40 Technical Information Manual

Chip set control

System memory

4
Technical Information
• 32 Kb Level 1 cache
• 64-bit microprocessor data bus
• 66 MHz front-side bus (FSB)
• Math coprocessor
• Internet Streaming SIMD extensions
• MMX technology, which boosts the processing of graphic, video, and audio data

L2 Cache

The Celeron microprocessor provides 128 KB L2 cache. The L2 cache error corrected
code (ECC) function is automatically enabled if ECC memory is installed. If nonparity
memory is installed, the L2 cache is non-ECC.
The SIS630 chip set design is the interface between the microprocessor and the
following:
• Memory subsystem
• Graphics subsystem
• PCI bus
• IDE bus master connection
• High performance, PCI-to-ISA bridge
• Audio controller
• Ethernet controller
• USB ports
• SMBus
• Enhanced DMA controller
• Real-time clock (RTC)
The maximum amount of system memory the computer can physically accommodate
is 512 MB total. The amount of system memory factory-preinstalled varies by model.
For memory expansion, the system board provides two dual inline memory module
(DIMM) connectors and supports 133 MHz DIMMs in sizes of 64 MB, 128 MB, and 256
MB.
The following information applies to system memory:
• Synchronous dynamic random access memory (SDRAM) is standard.
• The maximum height of memory modules is 6.35 cm (2.5 in.).
• Each DIMM installed must contain the same amount of memory.
• Non-parity, non-error-corrected code (non-ECC) DIMMs are standard.
• BIOS specific auto-configure, auto-detect maximum system memory.
For information on the pin assignments for the memory modules connectors, see
"System memory connector" on page 21.