Table 21. System memory connector pin input/output
Pin
Signal name
6
VDD
7
MD4
8
MD5
9
MD6
10
MD7
11
MD8 (PAR0)
12
GND
13
MD9
14
MD10
15
MD11
16
MD12
17
MD13
18
VDD
19
MD14
20
MD15
21
NC
22
NC
23
GND
24
NC
25
NC
26
VDD
27
WE#
28
DQMB0#
29
DQMB1#
30
S0#
31
OE0#
32
GND
33
A0
34
A2
35
A4
36
A6
37
A8
38
A10/AP
39
NC
40
VDD
24
Technical Information
I/O
Pin
I/O
90
I/O
91
I/O
92
I/O
93
I/O
94
I/O
95
N/A
96
I/O
97
I/O
98
I/O
99
I/O
100
I/O
101
N/A
102
I/O
103
I/O
104
I/O
105
I/O
106
I/O
107
N/A
108
N/A
109
N/A
110
I
111
I
112
I
113
I
114
I
115
N/A
116
I
117
I
118
I
119
I
120
I
121
I
122
123
N/A
124
Signal name
I/O
VDD
N/A
MD36
N/A
MD37
I/O
MD38
I/O
MD39
I/O
MD40
I/O
GND
N/A
MD41
I/O
MD42
I/O
MD43
I/O
MD44
I/O
MD45
I/O
VDD
N/A
MD46
I/O
MD47
I/O
NC
I/O
NC
I/O
GND
N/A
NC
N/A
NC
N/A
VDD
N/A
CAS#
N/A
DQMB4#
I
DQMB4#
I
S1#
I
RAS#
N/A
GND
N/A
A1
I
A3
I
A5
I
A7
I
A9
I
A11
I
NC
VDD
N/A