LG KU950 Service Manual page 166

7. CIRCUIT DIAGRAM
1 1 2 2
A A
B B
SDRAM_DATA[0:31]
SDRAM_DATA[0]
SDRAM_DATA[1]
SDRAM_DATA[2]
SDRAM_DATA[3]
SDRAM_DATA[4]
SDRAM_DATA[5]
SDRAM_DATA[6]
C C
SDRAM_DATA[7]
SDRAM_DATA[8]
SDRAM_DATA[9]
SDRAM_DATA[10]
SDRAM_DATA[11]
SDRAM_DATA[12]
SDRAM_DATA[13]
SDRAM_DATA[14]
SDRAM_DATA[15]
SDRAM_DATA[16]
SDRAM_DATA[17]
SDRAM_DATA[18]
SDRAM_DATA[19]
SDRAM_DATA[20]
SDRAM_DATA[21]
SDRAM_DATA[22]
SDRAM_DATA[23]
SDRAM_DATA[24]
SDRAM_DATA[25]
SDRAM_DATA[26]
D D
SDRAM_DATA[27]
SDRAM_DATA[28]
SDRAM_DATA[29]
SDRAM_DATA[30]
SDRAM_DATA[31]
SDRAM_DQM[0]
SDRAM_DQM[1]
SDRAM_DQM[2]
SDRAM_DQM[3]
EBI2_DATA[0:7]
EBI2_DATA[0]
EBI2_DATA[1]
EBI2_DATA[2]
EBI2_DATA[3]
EBI2_DATA[4]
EBI2_DATA[5]
EBI2_DATA[6]
EBI2_DATA[7]
E E
F F
G G
H H
1 1 2 2
3 3 4 4 5 5
MEMORY (1Gbit 90n NAND FLASH + 512Mbit SDRAM)
U4 C3
TP500 TP501
DQ0 A0
TP502 T4 D3
DQ1 A1
T5 E3
DQ2 A2
V5 E2
DQ3 A3
U5 D12
DQ4 A4
T6 C12
DQ5 A5
V6 D11
DQ6 A6
U7 C11
DQ7 A7
T9 D10
DQ8 A8
T10 C10
DQ9 A9
V10 E4 TP503 SDRAM_ADDR[10]
DQ10 A10
T11 D9 SDRAM_ADDR[11]
DQ11 A11
U11 C9 TP504 SDRAM_ADDR[12]
DQ12 A12
V11
DQ13
T12 L6
DQ14 _WP
U12 K6
DQ15 _WEN
TP505 P3 D5 TP506
DQ16 _RAS
R3 D6
TP507
DQ17 _WED
TP508 P4 E6 TP509
DQ18 _CAS
R4 C8
DQ19 CLK
P5 E5 TP510
DQ20 _CS
R5 M3 TP511
DQ21 ALE
P6 M4 TP512
DQ22 CLE
R6 M9
DQ23 _CE
P9 M10
DQ24 _RE
P10 M2
DQ25 RY__BY
R10 D8 TP513
DQ26 CKE
P11 C4
DQ27 BA0
R11 D4
DQ28 BA1
P12
DQ29
R12 C7
DQ30 VCCD1
R13 D2
DQ31 VCCD2
D13
VCCD3
TP514 U8 V3
DQM0 VCCD4
T8 V8
DQM1 U500 VCCD5
V7 V12
TP515
DQM2 VCCD6
U9
DQM3 TY9000A800EOGG
V4
VCCQD1
M11 V9
IO1 VCCQD2
M13
IO2
L10 K12
IO3 VCCN2
L12
IO4
J9 C6
IO5 VSS1
H12 F7
IO6 VSS2
H10 G2
IO7 VSS3
G12 G13
IO8 VSS4
L13
VSS5
A1 P2
NC1 VSS6
A2 P13
NC2 VSS7
A3 R8
NC3 VSS8
A4 U2
NC4 VSS9
A11 U6
NC5 VSS10
A12 U10
NC6 VSS11
A13 U13
NC7 VSS12
A14
NC8
B1 D7 R504
NC9 NC132
B2 J12
NC10 NC131
B3 K4
NC11 NC71
B4 K5
NC12 NC72
B11 K9
NC13 NC73
B12 K10
NC14 NC74
B13 K11
NC15 NC75
B14 K13
NC16 NC76
C1 K14
NC17 NC77
C2 L1
NC18 NC78
C5 L2
NC19 NC79
C13 L3
NC20 NC80
C14 L4
NC21 NC81
D1 L5
NC22 NC82
D14 L9
NC23 NC83
E1 L11
NC24 NC84
E7 L14
NC25 NC85
E8 M5
NC26 NC86
E9 M6
NC27 NC87
E10 M12
NC28 NC88
E11 N2
NC29 NC89
3 3 4 4 5 5
6 6 7 7 8 8
SDRAM_ADDR[0:12]
VREG_USIM_2.85V
SDRAM_ADDR[0]
D500
SDRAM_ADDR[1]
SDRAM_ADDR[2]
SDRAM_ADDR[3] 6
USIM_P_DATA
SDRAM_ADDR[4]
SDRAM_ADDR[5] 5
SDRAM_ADDR[6]
SDRAM_ADDR[7] 4
SDRAM_ADDR[8]
SDRAM_ADDR[9]
PLR0504F
RESOUT_N
USB_VBUS
D501
VREG_MSMP_2.7V
EBI2_WE_N
R501 6
SDRAM_RAS_N RMT_ADC/USB_D-
100K
SDRAM_WE_N
5
SDRAM_CAS_N
SDRAM_CLK
R502 R503 4
SDRAM_CS_N
NAND_ALE 100K 10K
NAND_CLE
PLR0504F
NAND_CS_N
EBI2_OE_N
NAND_READY
SDRAM_CLK_EN
VREG_MSME_1.8V
SDRAM_ADDR[13]
SDRAM_ADDR[14]
VREG_MSMP_2.7V
C512 C513
0.01u 0.1u
JTAG_PS_HOLD
RESET_IN_N
JTAG_TDO
NA
SDRAM_CS_N JTAG_RTCK
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TRST_N
6 6 7 7 8 8
- 167 -
9 9 10 10 11 11
VREG_USIM_2.85V
1
USIM_P_CLK
2
R500 4.7K
3
USIM_P_RST_N
J500
1 4
VCC GND
2 5
USIM_P_RST_N RST VPP
3 6
USIM_P_CLK CLK I_O
C500 C501 C502 C503 L500 C504
NA NA 0.1u 12p 1608 12p
56nH
1
RMT_INT/USB_D+
2
3
USIM
UART_TXD TP603
UART_RXD TP604
VREG_MSMP_2.7V PM_ON_SW_N TP605
UART5
CN500
CTS
G1 12
RTS
1 20 11
DSR
2 19 10
USB_D+ NC4 UTXD
3 18 9
TCC_RESET_JTAG_N USB_D- NC3 URXD
4 17 8
TCC_TDO USB_VBUS NC2 PWR
5 16 7
TCC_RTCK VBATT VBAT VBAT
6 15 6
TCC_TCK PM_ON_SW_N
ON_SW ON_SW
7 14 5
TCC_TMS NC1 UFLS
8 13 4
TCC_TDI UART_TXD TX TX
9 12 3
TCC_NTRST UART_RXD RX RX
10 11 2
GND GND
G2 1
R505 R506
2.5G 3G
NA 51K
PCB ARRAY TP
JTAG CONNECTOR
OJ500 OJ501 OJ502 OJ503 OJ504
Engineer: Engineer:
JH Park
Drawn by: Drawn by:
JH Park DEVELOPMENT LAB 4
R&D CHK: R&D CHK:
TITLE: TITLE:
DOC CTRL CHK: DOC CTRL CHK:
MFG ENGR CHK: MFG ENGR CHK:
Changed by: Changed by: Date Changed: Date Changed: Time Changed: Time Changed: QA CHK: QA CHK: REV: REV:
JH Park 2006, Sep 08 11:29:00 am
9 9 10 10 11 11
12 12
A A
B B
C C
USIM_P_DATA
D D
E E
F F
G G
H H
LG ELECTRONICS INC.
MOBILE HANDSET R&D CENTER
DEVELOPMENT GROUP 1
Size: Size:
A2 A2
KU950 MAIN 1.1
Drawing Number: Drawing Number:
Page: Page: 5/9
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