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7. CIRCUIT DIAGRAM
1
1
2
2
A
A
B
B
TCC_RESET_N
R402
0
TCC_RESET_JTAG_N
EBI2_DATA[0:15]
C
C
LCD_BYPASS_ENABLE
TCC_CS_N
EBI2_WE_N
EBI2_OE_N
TCC_INT
D
D
active HIGH
EBI2_ADDR[2]
EBI2_ADDR[1]
R420
MSM_LCD_ADS_N
100K
R425
E
E
100K
DIB_RESET_N
MSM_LCD_RESET_N
DIB_RDY
TCC_UART_TXD
TCC_UART_RXD
TCC_2.7V_MISC
R427
R428
NA
NA
F
F
DIB_PWR_EN
MM_LCD_VSYNC
G
G
TCC_TDO
TCC_TMS
TCC_RTCK
JTAG I/F
TCC_TCK
TCC_NTRST
H
H
1
1
2
2
3
3
4
4
5
5
TCC_1.2V_CORE
TCC_1.8V_SDR
TCC_2.7V_MISC
TCC_2.7V_EHI_LCD
C401
C400
12p
12p
Near to
TCC7820
TCC_2.7V_MISC
X400
DSX321G(12MHz,8PF)
3
4
2
1
12MHz
R401
R400
NA
100K
R404
NA
D1
HPXD17
F4
HPXD16
EBI2_DATA[15]
E2
HPXD15
EBI2_DATA[14]
F3
HPXD14
EBI2_DATA[13]
N1
HPXD13
EBI2_DATA[12]
F2
HPXD12
EBI2_DATA[11]
M2
HPXD11
EBI2_DATA[10]
E1
HPXD10
EBI2_DATA[9]
G2
HPXD9
EBI2_DATA[8]
G4
HPXD8
EBI2_DATA[7]
F1
HPXD7
EBI2_DATA[6]
K3
HPXD6
EBI2_DATA[5]
H2
HPXD5
EBI2_DATA[4]
H3
HPXD4
CSN_CS0
EBI2_DATA[3]
H4
HPXD3
CSN_CS1
EBI2_DATA[2]
G1
HPXD2
EBI2_DATA[1]
H5
HPXD1
EBI2_DATA[0]
J2
HPXD0
TP401
E3
BPEN
TP402
D2
HPCSN
L2
HPWRN
H6
HPRDN
J4
HPINT
TP404
H1
HPXA1
R418
0
J3
HPXA0
R419
NA
D13
HDDXD15
Internal pull down
E13
HDDXD14
F12
HDDXD13
G9
TCC_2.7V_MISC
HDDXD12
G10
HDDXD11
G8
HDDXD10
D15
HDDXD9
D14
HDDXD8
H9
U403
HDDXD7
R422
R423
E15
HDDXD6
H11
HDDXD5
TCC7820
4.7K
4.7K
E14
HDDXD4
H10
HDDXD3
F13
HDDXD2
F15
HDDXD1
J9
HDDXD0
A14
HDDCSN0
E12
HDDCSN1
B15
HDDIOR
A15
HDDIOW
R426
NA
E11
HDDAK
C14
HDDRQ
C13
HDDRDY
A13
HDDXA2
B14
HDDXA1
D12
HDDXA0
K15
UTXD0
J14
URXD0
J15
UCTS0
J13
URTS0
J12
UTXD1
G15
URXD1
H12
UCTS1
F14
URTS1
N15
GPA0_SCL
N14
GPA1_SDA
L14
GPA2
N13
GPA3
L13
GPA4
M15
GPA5
M14
R417
0
GPA6
M13
GPA7
D9
TP602
GPA8
C10
GPA9
N7
GPA10
N9
GPA11
R429
1M
TCC_TDI
DIB_IRQ
3
3
4
4
5
5
6
6
7
7
8
8
XA1
XA0
JTAG selection
0
0
ARM926
0
1
Test mode (Not used)
1
0
ARM946
1
1
ARM926 & ARM946
SRAM like I/F
TCC_2.7V_MISC
TCC_2.7V_MISC
P11
XD7
DIB_DATA[7]
N11
XD6
DIB_DATA[6]
M11
XD5
DIB_DATA[5]
R10
XD4
DIB_DATA[4]
N10
XD3
DIB_DATA[3]
M10
R409
XD2
DIB_DATA[2]
P10
XD1
DIB_DATA[1]
100K
M9
XD0
DIB_DATA[0]
R12
XA3
P12
XA2
N12
XA1
R11
XA0
R15
DIB_CS_N
DIB_ADDR[2]
R14
TP400
DIB_ADDR[1]
P15
WEN
DIB_WE_N
P14
OEN
DIB_OE_N
R416
10K
M7
VCKE
C2
LXD17
TP403
C4
LXD16
C5
LXD15
MM_LCD_DATA[15]
B5
LXD14
MM_LCD_DATA[14]
D5
LXD13
MM_LCD_DATA[13]
C6
LXD12
MM_LCD_DATA[12]
E4
LXD11
MM_LCD_DATA[11]
E5
LXD10
MM_LCD_DATA[10]
B4
LCD I/F
LXD9
MM_LCD_DATA[9]
B3
LXD8
MM_LCD_DATA[8]
K1
LXD7
MM_LCD_DATA[7]
J1
LXD6
MM_LCD_DATA[6]
A2
LXD5
MM_LCD_DATA[5]
B2
LXD4
MM_LCD_DATA[4]
L1
LXD3
MM_LCD_DATA[3]
G6
LXD2
MM_LCD_DATA[2]
B1
LXD1
MM_LCD_DATA[1]
K2
LXD0
MM_LCD_DATA[0]
D4
R424
NA
LCSN0
TCC_HOST_CS_N
C3
LCSN1
MM_LCD_CS_N
C1
LOEN
MM_LCD_RD_N
M1
LWEN
MM_LCD_WE_N
D3
LXA0
MM_LCD_ADS_N
D8
CPD7
B9
CPD6
C9
CPD5
B8
CPD4
E8
CPD3
A8
CPD2
C8
CPD1
A7
CPD0
F9
CCK
D10
CVS
B10
CHS
B11
CPWDN
TP406
P3
FRM0
P4
SCK0
M4
SDI0
R8
SDO0
M8
FRM1
P9
SCK1
P8
SDI1
R9
SDO1
P5
BCLK
BCLK
R3
LRCK
LRCK
CODEC I/F
N6
MCLK
MCLK
R4
DAO
DA_OUT
N5
DAI
P7
GPD22
N4
GPD23
R5
GPD24
6
6
7
7
8
8
- 166 -
9
9
10
10
11
11
TCC7820 Power
+VPWR
TCC_1.8V_SDR
L400
4.7uH
U400
AAT2510IWP-AA-T1
12
11
C420
100p
VIN1
LX1
9
2
R405
110K
C421
VIN2
FB1
4.7u
L401
4.7uH
1
8
EN1
LX2
4
5
C422
100p
TCC_PWR_EN
EN2
FB2
R408
56K
TCC_2.7V_MISC
+VPWR
U401
R1161N271D-TR-F
1
5
VDD
VOUT
2
GND
3
4
TCC_PWR_EN
CE
ECO
C427
C428
R421
2.2u
10K
1u
+VPWR
TCC_2.7V_EHI_LCD
U402
1
5
VDD
VOUT
2
GND
3
4
PS_HOLD
CE
NC
R1114N271D-TR-F
Always on state
Engineer:
Engineer:
LG ELECTRONICS INC.
JH Park
MOBILE HANDSET R&D CENTER
Drawn by:
Drawn by:
JH Park
DEVELOPMENT LAB 4
R&D CHK:
R&D CHK:
TITLE:
TITLE:
DOC CTRL CHK:
DOC CTRL CHK:
MFG ENGR CHK:
MFG ENGR CHK:
Changed by:
Changed by:
Date Changed:
Date Changed:
Time Changed:
Time Changed:
QA CHK:
QA CHK:
REV:
REV:
JH Park
2006, Sep 08
11:14:00 am
9
9
10
10
11
11
12
12
A
A
B
B
TCC_1.2V_CORE
C
C
D
D
E
E
F
F
G
G
H
H
DEVELOPMENT GROUP 1
Size:
Size:
A2
A2
KU950 Main 1.1
Drawing Number:
Drawing Number:
Page:
Page:
4/9
12
12
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