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7. CIRCUIT DIAGRAM
1
1
2
2
A
A
OUT200
SW200
C200
7p
R200
G2
ANT
RF
G1
0
KMS-507
C201
L200
L201
NA
15nH
NA
+2.7V_DIB_RF
B
B
C213
C214
C217
C218
1000p
10p
1000p
10p
+2.7V_DIB_RF
R205
47
C227
C226
C230
C229
1000p
1000p
10p
10p
C
C
1
2
L203
C236
3
RFIN
10nH
4
1000p
5
6
WBD_OUT
7
8
9
C239
L204
10
33nH
1u
C247
220n
C248
R215
1.5K
2200p
+2.7V_DIB_RF
(1%)
D
D
C252
C253
C255
C256
1000p
1000p
10p
10p
E
E
+VPWR
F
F
U202
1
5
VDD
VOUT
2
GND
3
4
DIB_PWR_EN
CE
NC
R1114N181D-TR-F
C261
1608
1u
+1.8V_SRAM
TCC_1.8V_SDR
G
G
U205
1
VDD
VOUT
2
GND
3
DIB_PWR_EN
CE
NC
R1131N121D-TR-F
C267
1u
1608
H
H
1
1
2
2
3
3
4
4
5
5
FL200
F5024
5
1
RFIN
I_O1
I_O2
R201
100p
2
8
G1
G6
G2 G3 G4 G5
C202
C203
NA
NA
+2.7V_DIB_RF
C219
C215
C220
C216
10p
1000p
10p
1000p
C221
0.01u
+2.7V_DIB_RF
C222
1u
C223
20p
C231
C228
10p
1000p
30
+2.7V_DIB_A
RFIN_LBAND
GND4
29
R207
10K
GND1
RF_AGC
RF_AGC
28
RFIN_UHF
BB_AGC
BB_AGC
27
R208
10K
GND2
BB_VCC
26
C237
C238
RF_VCC
U200
GND3
25
R209
0
PDOUT
MT2260
BB_IN
INO
22n
22n
24
R210
0
BB_IP
DAC_GPO
IPO
23
R212
0
LOAVCC
BB_QN
QNO
22
R213
0
LOREG
BB_QP
QPO
21
LOLPF
PWR_DN
+2.7V_DIB_RF
C249
1u
R216
390
DIB_I2C_SCL
DIB_I2C_SDA
R217
390
C257
X201 FA-238_30M_99PF
C258
4
3
22p
22p
1
2
30MHz
MT2260
DVB-H RF tuner
POWER for DVB-H part
+1.8V_SRAM
+VPWR
+2.7V_DIB_RF
U203
1
5
VDD
VOUT
2
GND
3
4
DIB_PWR_EN
CE
ECO
R1161N271D-TR-F
R220
10K
C259
1u
C262
1608
1608
1u
+2.7V_DVB_RF
+VPWR
U206
5
1
5
VDD
VOUT
2
GND
4
3
4
DIB_PWR_EN
CE
NC
R1114N271D-TR-F
C264
1u
C265
1u
1608
1608
+2.7V_A_OSC
3
3
4
4
5
5
6
6
7
7
8
8
TCC_1.2V_CORE
+1.2V_DIB_CORE
+1.2V_DIB_PLL
+2.7V_DIB_OSC
FB200
R202
100ohm
R203
100ohm
R204
1M
A2
VDDXO
1608 1%
A3
VDDXI
B4
X200
XOUT
A4
4
3
XIN
A6
1
2
PLL_VCC
C6
30MHz
PLL_GND
L3
EXXY0015502
C224
CLK_SEL
FA-238_30MHz
L1
20p
IO_CLK
H2
C225
XENA
B12
INO
VINNI
B11
0.1u
IPO
VINPI
B8
C232
QNO
VINNQ
B9
0.1u
QPO
VINPQ
A12
C233
VREFN
A11
VREFP
C234
0.1u
A13
+1.2V_DIB_A
0.1u
VCM
C235
0.1u
A14
DIB7000-H
VBG
B13
AVDD1
C11
AGND1
C12
AGNDREF
A8
AVDDIQ
A9
AVDD3V3
C9
AGNDIQ
B5
VIN0
B6
C240
C241
C242
C243
C244
C245
C246
WBD_OUT
VIN1
B7
1u
0.1u
1u
0.1u
1u
0.1u
0.1u
VIN2
A7
1608
1608
1608
AVDD_LS
C7
AGND_LS
F1
VDD_BANK0
E1
AGC1
E3
FB202 75
AGC2
E2
SCL_MASTER
F2
SDA_MASTER
RF_AGC
C250
C251
BB_AGC
DIB_I2C_SCL
4.7u
0.1u
DIB_I2C_SDA
+2.7V_DIB_RF
EUSY0275001
DVB-H BB Module
A3
SRAM_ADDR[0]
A4
SRAM_ADDR[1]
A5
SRAM_ADDR[2]
B3
SRAM_ADDR[3]
B4
SRAM_ADDR[4]
C3
SRAM_ADDR[5]
C4
SRAM_ADDR[6]
D4
SRAM_ADDR[7]
H2
SRAM_ADDR[8]
H3
C260
SRAM_ADDR[9]
H4
1u
SRAM_ADDR[10]
H5
SRAM_ADDR[11]
G3
SRAM_ADDR[12]
G4
SRAM_ADDR[13]
F3
SRAM_ADDR[14]
F4
SRAM_ADDR[15]
E4
SRAM_ADDR[16]
+1.8V_SRAM
D3
SRAM_ADDR[17]
H1
SRAM_ADDR[18]
D6
E1
B5
C263
SRAM_CE1_N
A6
+1.8V_SRAM
0.1u
G5
SRAM_WE_N
A2
SRAM_OE_N
A1
SRAM_LB_N
B2
SRAM_UB_N
DVB-H SRAM
C266
1u
1608
6
6
7
7
8
8
- 164 -
9
9
10
10
11
11
INT_SELECT1
INT_SELECT0
Host Interface Type
0
0
SRAM like
0
1
SPI or SD (1 and 4 bits)
TCC_2.7V_MISC
1
0
I2C Control
1
1
C212
0.1u
R6
VDD_BANK1
G2
RESETN
DIB_RESET_N
Option : HIGH (SDIO)
M3
GPIO_BUS1
N4
GPIO_BUS2
G1
INT_SELECT0
Default : GND (SRAM like)
G3
INT_SELECT1
M1
DIB_OE_N
HOST_BUS0
M2
DIB_CS_N
HOST_BUS1
N1
DIB_WE_N
HOST_BUS2
N2
DIB_ADDR[1]
HOST_BUS3
P1
DIB_ADDR[2]
HOST_BUS4
P3
HOST_BUS5
DIB_DATA[0]
N5
HOST_BUS6
DIB_DATA[1]
U201
R2
HOST_BUS7
DIB_DATA[2]
P4
HOST_BUS8
DIB_DATA[3]
R3
HOST_BUS9
DIB_DATA[4]
P5
HOST_BUS10
DIB_DATA[5]
R4
HOST_BUS11
DIB_DATA[6]
P6
HOST_BUS12
DIB_DATA[7]
R5
HOST_BUS13
DIB_RDY
P7
HOST_BUS14
DIB_IRQ
R8
VDD_BANK2_1
D15
VDD_BANK2_2
R211
D14
GPIO_BUS3
C15
10K
GPIO_BUS4
E15
SRAM_BUS40
SRAM_OE_N
E14
R214
0
TCC_2.7V_MISC
SRAM_BUS39
SRAM_CE1_N
E13
SRAM_BUS38
SRAM_ADDR[0]
F15
SRAM_BUS37
SRAM_LB_N
F14
SRAM_BUS36
SRAM_DATA[1]
F13
SRAM_BUS35
SRAM_ADDR[1]
G15
+1.8V_SRAM
SRAM_BUS34
SRAM_UB_N
G14
SRAM_BUS33
SRAM_ADDR[4]
C254
0.1u
U204
K6F8016R6D-XF70
A0
G2
A1
DNU1
H6
A2
DNU2
A3
A4
A5
B6
A6
IO1
SRAM_DATA[0]
C5
A7
IO2
SRAM_DATA[1]
C6
A8
IO3
SRAM_DATA[2]
D5
A9
IO4
SRAM_DATA[3]
E5
A10
IO5
SRAM_DATA[4]
F5
A11
IO6
SRAM_DATA[5]
F6
A12
IO7
SRAM_DATA[6]
G6
A13
IO8
SRAM_DATA[7]
B1
A14
IO9
SRAM_DATA[8]
C1
A15
IO10
SRAM_DATA[9]
C2
A16
IO11
SRAM_DATA[10]
D2
A17
IO12
SRAM_DATA[11]
E2
A18
IO13
SRAM_DATA[12]
F2
IO14
SRAM_DATA[13]
F1
IO15
SRAM_DATA[14]
G1
VCC1
IO16
SRAM_DATA[15]
VCC2
_CS1
CS2
D1
_WE
VSS1
E3
_OE
VSS2
E6
_LB
VSS3
_UB
EUSY0278001
Engineer:
Engineer:
Shawn Shin
Drawn by:
Drawn by:
Shawn Shin
DEVELOPMENT LAB 4
R&D CHK:
R&D CHK:
TITLE:
TITLE:
DOC CTRL CHK:
DOC CTRL CHK:
MFG ENGR CHK:
MFG ENGR CHK:
Changed by:
Changed by:
Date Changed:
Date Changed:
Time Changed:
Time Changed:
QA CHK:
QA CHK:
REV:
REV:
Shawn Shin
2006, Sep 08
10:04:00 am
9
9
10
10
11
11
12
12
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
LG ELECTRONICS INC.
MOBILE HANDSET R&D CENTER
DEVELOPMENT GROUP 1
Size:
Size:
A2
A2
KU950 Main 1.1
Drawing Number:
Drawing Number:
Page:
Page:
2/9
12
12
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Table of Contents
Troubleshooting
