Fixed I/O Map; I/O Map - Intel BLKD101GGCL Specification

2.3 Fixed I/O Map

Table 11.

I/O Map

Address (hex)
0000 - 00FF
0170 - 0177
01F0 - 01F7
(Note 1)
0228 - 022F
(Note 1)
0278 - 027F
(Note 1)
02E8 - 02EF
(Note 1)
02F8 - 02FF
0374 - 0377
0377, bits 6:0
0378 - 037F
03E8 - 03EF
03F0 - 03F5
03F6 – 03F7
03F8 - 03FF
04D0 - 04D1
LPTn + 400
(Note 2)
0CF8 - 0CFB
(Note 3)
0CF9
0CFC - 0CFF
FB00 – FB07
FB08 – FB0F
Notes:
1. Default, but can be changed to another address range
2. Dword access only
3. Byte access only
NOTE
Some additional I/O addresses are not available due to IXP 450 address aliasing. The IXP 450
data sheet provides more information on address aliasing.
Size Description
256 bytes Used by the Desktop Board D101GGC. Refer to the
IXP 450 data sheet for dynamic addressing information.
8 bytes Secondary Parallel ATA IDE channel command block
8 bytes Primary Parallel ATA IDE channel command block
8 bytes LPT3
8 bytes LPT2
8 bytes COM4
8 bytes COM2
4 bytes Secondary Parallel ATA IDE channel control block
7 bits Secondary IDE channel status port
8 bytes LPT1
8 bytes COM3
6 bytes Diskette channel
1 byte Primary Parallel ATA IDE channel control block
8 bytes COM1
2 bytes Edge/level triggered PIC
8 bytes ECP port, LPTn base address + 400h
4 bytes PCI Conventional bus configuration address register
1 byte Reset control register
4 bytes PCI Conventional bus configuration data register
8 bytes Primary Parallel ATA IDE bus master registers
8 bytes Secondary Parallel ATA IDE bus master registers
Technical Reference
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