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(6)
Read/write circuit
The read/write circuit utilizes a read channel mounted with a head IC that supports high-speed
transmission and an MEEPR4ML (Modified Enhanced Extended Partial Response Class 4
Maximum Likelihood) modulation/demodulation circuit in order to prevent errors being triggered
by external noise and to improve data reliability.
(7)
Controller circuit
The controller circuit uses LSIs to increase the reliability and uses a high speed microprocessing
unit (MPU) to increase the performance of the SCSI controller.
1.3
System Configuration
Figure 1.4 shows the system configuration. The IDDs are connected to the SCSI bus of host
systems and are always operated as target. The IDDs perform input/output operation as specified
by SCSI devices which operate as initiator.
1 - 8
SCSI bus
Figure 1.4
System configuration
C141-E128-01EN
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Troubleshooting
