Idle Power Management Breakdown Of The Processor Cores; Thread And Core C-State Entry And Exit - Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet

Power Management
Figure 4-1.

Idle Power Management Breakdown of the Processor Cores

Entry and exit of the C-States at the thread and core level are shown in
Figure 4-2.

Thread and Core C-State Entry and Exit

C1
While individual threads can request low power C-states, power saving actions only
take place once the core C-state is resolved. Core C-states are automatically resolved
by the processor. For thread and core C-states, a transition to and from C0 is required
before entering any other C-state.
Datasheet, Volume 1
Thread 0 Thread 1
Core 0 State
Processor Package State
MWAIT(C1), HLT
MWAIT(C1), HLT
(C1E Enabled)
P_LVL2 I/O Read
C1E
Thread 0 Thread 1
Core 1 State
C0 C0
MWAIT(C6),
P_LVL3 I/O Read
MWAIT(C3),
C3 C6
Figure 4-2.
MWAIT(C 7),
P_LVL4 I/O Read
C7
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