Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet page 6

6.13 Sense Pins ........................................................................................................84
6.14 Ground and NCTF ..............................................................................................85
6.15 Future Compatibility...........................................................................................85
6.16 Processor Internal Pull Up/Pull Down ....................................................................85
7 Electrical Specifications ...........................................................................................87
7.1 Power and Ground Pins.......................................................................................87
7.2 Decoupling Guidelines ........................................................................................87
7.2.1 Voltage Rail Decoupling ...........................................................................87
7.2.2 PLL Power Supply ...................................................................................87
7.3 Voltage Identification (VID).................................................................................88
7.4 System Agent (SA) V
7.5 Reserved or Unused Signals ................................................................................92
7.6 Signal Groups ...................................................................................................93
7.7 Test Access Port (TAP) Connection .......................................................................95
7.8 Storage Condition Specifications ..........................................................................95
7.9 DC Specifications ...............................................................................................96
7.9.1 Voltage and Current Specifications ............................................................97
7.10 Platform Environmental Control Interface (PECI) DC Specifications ......................... 103
7.10.1 PECI Bus Architecture............................................................................ 103
7.10.2 PECI DC Characteristics ......................................................................... 104
7.10.3 Input Device Hysteresis ......................................................................... 105
8 Processor Pin and Signal Information .................................................................... 107
8.1 Processor Pin As signments ............................................................................... 107
8.2 Package Mechanical Information ........................................................................ 157
9 DDR Data Swizzling................................................................................................ 169
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VID ................................................................................92
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Datasheet, Volume 1