Package C7 State; Dynamic L3 Cache Sizing; Imc Power Management; Disabling Unused System Memory Outputs - Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet

Power Management
4.2.5.5

Package C7 State

The processor enters the package C7 low power state when all cores are in the C7 state
and the L3 cache is completely flushed. The last core to enter the C7 state begins to
shrink the L3 cache by N-ways until the entire L3 cache has been emptied. This allows
further power savings.
Core break events are handled the same way as in package C3 or C6. However, snoops
are not sent to the processor in package C7 state because the platform, by granting the
package C7 state, has acknowledged that the processor possesses no snoopable
information. This allows the processor to remain in this low power state and maximize
its power savings.
Upon exit of the package C7 state, the L3 cache is not immediately re-enabled. It
re-enables once the processor has stayed out of C6 or C7 for an preset amount of time.
Power is saved since this prevents the L3 cache from being re-populated only to be
immediately flushed again.
4.2.5.6

Dynamic L3 Cache Sizing

Upon entry into the package C7 state, the L3 cache is reduced by N-ways until it is
completely flushed. The number of ways, N, is dynamically chosen per concurrent C7
entry. Similarly, upon exit, the L3 cache is gradually expanded based on internal
heuristics.
4.3

IMC Power Management

The main memory is power managed during normal operation and in low-power ACPI
Cx states.
4.3.1

Disabling Unused System Memory Outputs

Any system memory (SM) interface signal that goes to a memory module connector in
which it is not connected to any actual memory devices (such as SO-DIMM connector is
unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM
signals are:
• Reduced power consumption.
• Reduced possible overshoot/undershoot signal quality issues seen by the processor
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
When a given rank is not populated, the corresponding chip select and CKE signals are
not driven.
At reset, all rows must be assumed to be populated, until it can be proven that they are
not populated. This is due to the fact that when CKE is tristated with an SO-DIMM
present, the SO-DIMM is not ensured to maintain data integrity.
SCKE tri-state should be enabled by BIOS where appropriate, since at reset all rows
must be assumed to be populated.
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