Dram Timing Settings - JETWAY V333DAR2A User Manual

DRAM Timing Settings

Please refer to section 3-6-1
AGP Timing Settings
Please refer to section 3-6-2
PCI Timing Settings
Please refer to section 3-6-3
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Video RAM Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The
settings are: Enabled and Disabled.
Memory Hole
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area
of system memory usually discusses their memory requirements. The settings are: Enabled
and Disabled.
3-6-1 DRAM Timing Settings
CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
Auto Configuration
RAS Active Time
RAS Precharge Time
RAS to CAS Delay
CAS Latency
Bank Interleave
DRAM Command Rate
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
RAS Active Time
This field let's you insert a timing delay between the CAS and RAS strobe signals, used
when DRAM is written to, read from, or refreshed. Fast gives faster performance; and
Slow gives more stable performance. This field applies only when synchronous DRAM is
installed in the system. The settings are: 2T and 3T.
DRAM Timing Settings
Optimized
6T
3T
3T
2.5T
4 Bank
2T Command
F6:Optimized Defaults
26
Item Help
Menu Level >>
F1:General Help
F7:Standard Defaults