Dram Timing Settings - JETWAY K8M8MSR1A User Manual

Video RAM Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The settings
are: Enabled and Disabled.
Memory Hole
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements. The settings are: Enabled and
Disabled.

3-6-1 DRAM Timing Settings

Hypertransport Link Frequency
HYpertransport Link Width in
Hypertransport Link Width Out
Auto Configuration
x DRAM CAS Latency
x RAS Active Time
x RAS Precharge Time
x RAS to CAS Delay
x Bank Interleave
DRAM Command Rate
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
RAS Active Time
This field let's you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2T and 3T.
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.
CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Timing Settings
800 MHz
16 bit
16 bit
Auto
CL=2.5
8 Bus Clocks
3 Bus Clocks
3 Bus Clocks
Enabled
1T(By CPU)
F6:Optimized Defaults
Menu Level >>
F7:Standard Defaults
24
Item Help
F1:General Help