Dram Timing Settings - JETWAY 939TURBOR208 User Manual

3-6-1 DRAM Timing Settings

Timing Mode
DRAM CAS Latency
SDRAM Cycle Time
SDRAM RAS-to-CAS Delay
SDRAM Precharge Time
MTRR Mapping Mode
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
SDRAM RAS-to-CAS Delay
This field let's you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 4T and 3T.
SDRAM Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.
DRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Timing Settings
Auto
2.5T
8T
4T
2T
Continuous
F6:Optimized Defaults
Menu Level >>
F7:Standard Defaults
26
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