Sdram Cycle Length; Dram Clock - TYAN TIGER 133 Manual

Chipset Features Setup - Optimized Default Settings
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Bank 0/1 DRAM Timing
Bank 2/3 DRAM Timing
Bank 4/5 DRAM Timing
Bank 6/7 DRAM Timing

SDRAM Cycle Length

DRAM Clock

Memory Hole
P2C/C2P Concurrency
Fast R-W Turn Around
System BIOS Cacheable
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AGP Aperature Size
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Memory Parity/ECC Check
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F5:Previous Values
Bank 0/1, 2/3, 4/5, 6/7 DRAM Timing
The system board designer must select the proper value for these fields,
according to the specifications of the installed DRAM chips. Turbo mode
reduces CAS access time by 1 clock tick.
SDRAM Cycle Length
This field sets the CAS latency timing.
DRAM Clock
Allows you to set the memory clock speed to either 66MHz or equal to the
CPU clock speed, depending on your memory speed.
S1834 Tiger 133
Advanced Chipset Features
SDRAM 10ns
SDRAM 10ns
SDRAM 10ns
SDRAM 10ns
3
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