Program Testing; Instruction (I) Cycle - IBM 1620 1 Manual

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Thorough documentation and preparation should pre-
cede the testing of all programs. Careful console oper-
ation is next in importance. The following console
operating procedures are helpful in analyzing pro-
grams in the computer.
Instruction
(lJ
Cycle
Pressing the Instant Stop/seE key stops the computer
at the end of the machine cycle in operation at the
time the key is pressed. Successive depressions of the
key step the computer through
2O-fLsec
machine
cycles. The I and E cycle console lights show the
progression of an instruction that is executed with
each depression of the seE key.
Eight depressions of the seE key step the computer
completely through the eight machine cycles of the
I cycle of any instruction. During the I cycle, the fol-
lowing MARS registers are read into:
Operation (Op) Register - instruction code.
Instruction Address Register 1 (IR-I) - address
of next instruction.
MARS
IR-l
-
MAR
-
OR-l
-
~
OR-2
Incr/Decr
Switch
~
MBR
0
E
" - - -
r---
'-f-'
.-
Figure 57.
Diagram of I Cycle
Program Testing
Operand Address Register 1 (OR-I) - Q address
of the instruction in the Op register.
Operand Address Register 2 (OR-2) - P address
of the instruction in the Op register.
Pressing the Reset key puts the computer in manual
mode.
Alternate depressions of the Display MAR key and
positioning of the MARS Display switch (they must
not occur simultaneously) show the operator the ad-
dresses of P and
Q
data. Once the location of the
data is known, a Write instruction inserted at 00000
can be used to cause data to print.
Figure 57 shows that both IR-I and MAR are involv-
ed in the reading of an instruction from core storage.
At the beginning of the I cycle, IR-I contains the
address of the first operation code digit, 00, of the
instruction.
During the first machine cycle, the address contain-
ed in IR-I is placed in MAR. The two-digit operation
code of the instruction is moved from core storage to
MBR-E and MBR-O and transmitted to the two-digit
operation register. Simultaneously, the contents of
Core Storage
lop I p I
Q
J
~
" ' - - - -
---
67

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