IBM 1620 1 Manual page 31

position of the resulting field. An existing flag bit
at the Q address is retained for algebraic sign; the
field flag bit is transmitted with the high-order digit
of the Q field (Figure 31).
Core Storage Locations
Care Storage Locations
01590_01599
Instruction
01590-01599
Before
After
"' "
I
Ep
I
Mq
I
Eq OP
I
P
I
Q
"'" I
Ep
1
Mq
I
Eq
i
2 310 210 7 810 5
o
510 1 5 9 510 1 5 9 7 1231021780105
Figure 31. Floating Shift Left
If the mantissa is expanded to a length greater
than 2L, any extraneous flag bits in core storage
positions between the old high-order position and the
new low-order position of the mantissa must be
cleared before the FSL instruction is given. There-
fore, if Q - P is equal to or greater than 2L, loca-
tions P
+
L through Q -
L must be free of flags.
Contrary to other instructions in the floating-point
series, FSL is executed in the transmit record manner
of transmitting individual digits in the high-order to
low-order sequence. After the units digit has been
transmitted, the positions of the expanded mantissa
are set to zero, in ascending core storage location
sequence. After each position is set to zero, the suc-
ceeding position is checked for a flag bit. If the
fraction is positive, the flag bit is assumed to be the
high-order position of the exponent and the operation
stops without altering the flag bit position.
If
the
fraction is negative, the flag bit is assumed to be
the units position of the fraction, and a negative zero
is inserted in the units position before the operation
stops. Thus, a flag bit detected prior to the previous
high-order position of the mantissa stops the opera-
tion and results in an incorrect mantissa.
For example, if P
==
01590, Q
==
01601, and L
==
4,
core storage locations 01590 through 01603, with an
extraneous flag bit in 01596, appear as follows:
XXXXXXXXMMMMEE
After transfer of the mantissa, but before the zero-
fill operation, the core storage locations appear as
follows (not that the flag bit in 01598 has been
cleared) :
MMMMXXXXMMMMEE
Upon completion of the operation, the mantissa is
incorrect, as follows:
MMMMOOXXMMMMEE
If 01596 had not contained a flag bit, the mantissa
would have been expanded correctly, as follows:
MMMMOOOOOOOOEE
Execution Time. T
==
200
+
40L
+
40L' fLsec.
(L'
==
length mantissa is increased by shift.)
Transmit Floating (TFL-06)
Description. The field at the
Q
address is trans-
mitted to the location designated by the P address.
Mq and Eq are not altered in core storage. The Q
address is normally the low-order position of the
exponent, and the operation is the same as the regular
Transmit Field instruction (TF -26), except that flag
bits in the three low-order positions are ignored as
indications to terminate the transmission. Beginning
with the fourth low-order digit, a flag bit terminates
the operation. All flag bits in the field are transmitted
(Figure 32).
Execution Time. T
==
240
+
4OL.
Core Storage Locations
Core Storage Locations
01590-01599
I nstruct ion
01590-01599
Before After
"' "
I
Ep
I
Mq
I
Eq OP
I
P
I
Q
"",!EpIMqLEq
1 2 3\0 217 8 910 5
o
610 1 5 9 410 1 5 9 9
"7
8 910 5/7 8 910 5
Figure 32. Transmit Floating
Branch and Transmit Floating (BTSF-07l
Description. The address of the next instruction is
saved in IR-2, and the field at the Q address is trans-
mitted to the P address minus one. The instruction at
the P address is the next one executed. Mq and Eq are
not altered in core storage. The Q address is normally
the low-order position of the exponent. The operation
is the same as the regular Branch and Transmit
instruction (BT -27), except that in the transmit
function the three low-order position flags are ignored
as indications to terminate the transmission. Beginning
·with the fourth low-order position, a flag bit termi-
nates the operation. All flag bits are transmitted.
Execution Time: T
==
280
+
40L fLsec.
Mantissa
and Exponent
Analysis
Zero Mantissa
When a floating-point computation results in a zero
mantissa, a special floating-point zero is created in the
27