IBM 1620 1 Manual page 14

length because the flag bit over the units position of
the P address also defines the end of the immediate
data.
Execution Time. Each address interpreted as an
indirect address requires four additional
20-ftsec
mem-
ory cycles. For example, an instruction with two
indirect addresses requires an additional 160 ftsec.
Examples
The Add instruction, 21 00500 00650, is shown in
Figure 8 with both direct and indirect
Q
addresses.
Line 1 shows direct addressing; the Q data is obtained
from the Q address. Line 2 shows the Q address as
indirect; the
Q
data is obtained from the address
specified by the indirect address. Line 3 shows that
the address specified by the indirect address is also
indirect; the
Q
data is obtained from the address
specified by the second indirect address.
The data flow diagram for an Add Immediate in-
struction, 11 00500 00650, is shown in Figure 9. The
Q data 000650, is added to the data at the address
specified by the indirect P address. The result,
1155078, replaces the original P data, 1154428, at
09400.
A data flow diagram for a Branch instruction is
shown in Figure 10. The first five digits at that in-
direct address are the address to which the computer
branches for its next instruction.
Instructions
Data at Storage Locations Resultant Modified
Actual
Q
Actual
Q
00650 1 5225 12500
0)2 1 00500 00650 1 5225
@21 00500 00650 15225 12500
@21 00500 00650 15225 12500
12345
Figure 8. Examples of Indirect Addressing
OP
Code
Dr:
p
T
Q~
500': 00650
~
I, I
Y
I
I
I
II
&
10 9400
i
2 1
(0)2 1
(b) 2 1
{6 Digits Maximum}
00065
1 15442
1 15507
0
8
8
Figure 9, Indirect Addressing, Add Immediate Instruction
10
Instruction
Address
Data
Used Used
00650 15225
00500 15225
1 5225 125.00
00500 15225
00500 12500 12500 12345
CORE STORAGE
\:)/.
~Af}
IT
1 54428
~
L
Add
Table
t - - -
..