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Table 8-1. Supported Functionality by Operating Mode (continued)
OPERATING MODE
TRNG
ADC0, ADC1
DAC0
OPA0, OPA1
Analog
GPAMP
COMP0,
COMP1,
COMP2
IOMUX and IO Wakeup
Wake Sources
(1)
If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as in RUN1 and
ULPCLK remains at 32 kHz as in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from
LFCLK), SYSOSC remains disabled as in RUN2 and ULPCLK remains at 32 kHz as in RUN2.
(2)
When using the STANDBY1 policy for STANDBY, only TIMG0, TIMG8, and the RTC are clocked. Other PD0 peripherals can generate
an asynchronous fast clock request upon external activity, but the peripherals are not actively clocked.
(3)
For ADCx and GPIO Ports A and B, the digital logic is in PD0 and the register interface is in PD1. These peripherals support fast
single-cycle register access when PD1 is active and also support basic operation down to STANDBY mode where PD0 is still active.
8.3 Power Management Unit (PMU)
The power management unit (PMU) generates the internally regulated core supplies for the device and provides
supervision of the external supply (VDD). The PMU also contains the bandgap voltage reference used by the
PMU itself as well as analog peripherals. Key features of the PMU include:
•
Power-on reset (POR) supply monitor
•
Brown-out reset (BOR) supply monitor with early warning capability using three programmable thresholds
•
Core regulator with support for RUN, SLEEP, STOP, and STANDBY operating modes to dynamically balance
performance with power consumption
•
Parity-protected trim to immediately generate a power-on reset (POR) in the event that a power management
trim is corrupted
For more details, see the PMU chapter of the
Manual.
8.4 Clock Module (CKM)
The clock module provides the following oscillators:
•
LFOSC: Internal low-frequency oscillator (32 kHz)
•
SYSOSC: Internal high-frequency oscillator (4 MHz or 32 MHz with factory trim, 16 MHz or 24 MHz with user
trim)
•
LFXT/LFCKIN : Low-frequency external crystal oscillator or digital clock input (32 kHz)
•
HFXT/HFCKIN: High-frequency external crystal oscillator or digital clock input (4 to 48 MHz)
•
SYSPLL: System phase locked loop with 3 outputs (32 to 80 MHz)
The following clocks are distributed by the clock module for use by the processor, bus, and peripherals:
•
MCLK: Main system clock for PD1 peripherals, derived from SYSOSC, LFCLK, or HSCLK, active in RUN and
SLEEP modes
•
CPUCLK: Clock for the processor (derived from MCLK), active in RUN mode
•
ULPCLK: Ultra-low power clock for PD0 peripherals, active in RUN, SLEEP, STOP, and STANDBY modes
Copyright © 2023 Texas Instruments Incorporated
RUN
OPT
(3)
OPT
NS
OPT
OPT
OPT
OPT
(ULP)
N/A
MSPM0 G-Series 80-MHz Microcontrollers Technical Reference
Product Folder Links:
MSPM0G1507 MSPM0G1506 MSPM0G1505
MSPM0G1507, MSPM0G1506, MSPM0G1505
SLASEW9B – FEBRUARY 2023 – REVISED AUGUST 2023
SLEEP
STOP
OPT
OPT
NS
OPT
OPT
OPT
OPT
(ULP)
EN
ANY IRQ
STANDBY
OFF
NS (triggers supported)
OFF
NS
OFF
NS
OFF
NS
OFF
OPT
OFF
(ULP)
DIS w/
WAKE
IOMUX,
PD0 IRQ
NRST, SWD
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