Philips 32HFL5662L/F7 Service Manual page 33

8.3 Diagram B01 SMB: 32-bit DDR
Block diagram
2 HDMI
Component 1
Component 2
Component 3
Svideo 1
Svideo 2
Svideo 3
RGB + HV
Composite 1
Composite 2
Composite 3
Composite 4
SIF
ITU 656
DS_IF
I2S
SPDIF
Audio
Switch
6 Audio L/R
and A/D
Term/Conn, BCM3549L (IC U1)
Dual HDMI
Receiver
Video Front
End
5x 10bit A/Ds
NTSC Video Decoders
VBI Decoder
NTSC/PAL/SECAM
Demod +
12bit A/D
BTSC Decoder
A2 Decoder
QAM/VSB Demod
Figure 8-4 Internal block diagram
IC Data Sheets
3D
Comb
Video & Graphics
Processing (BVN)
HD Analog Noise
Reduction
Digital Noise Reduction
Picture Enhancement
Processor
Motion Adaptive
1080i De-interlacing
AVC/MPEG 4/VC-1/MPEG 2
Programmable
Audio
DSP
AVC/MPEG 4/VC-1/MPEG 2
Transport Processor
with DVB/DES
EIA/CEA
909
TPB1.1HU LA
Peripherals
Keypad LED
GPIO
3D Graphics
3 UARTS
Dual USB 2.0
Ethernet
JPEG Decoder DVR Engine
2x Video
DACs
HD/SD Video
Encoder
HD/SD Video Decoder
Audio
DACs
MIPS DUAL CORES
32KI/32KI & 64KD
128KB L2
400MHz
DDR2 Memory
SPI & Nand
Interface 32 bits
Flash Interfaces
– 800/1066 MHz
8. EN 33
2
Svideo, CVBS
ITU656
Dual LVDS
L/R Audio
L/R Audio
L/R Audio
SPDIF
I2S (dual)
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101008
2010-Nov-05