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Chapter 3
Signal Connections
Parameter
Tgatepw
Note
For buffered measurements, the minimum period required for the CtrnGate signal is
determined by how fast the system can transfer data from your device to computer memory.
Counter n Auxiliary Signal
NI 660x User Manual
You can export the CtrnGate signal to the I/O connector's default PFI input
for each CtrnGate. For example, you can export the gate signal connected
to counter 0 to the PFI 38/CTR 0 GATE pin, even if another PFI is inputting
the Ctr0Gate signal. This output is set to high-impedance at startup.
Figure 3-6 shows the timing requirements for the CtrnGate signal.
Ctr n Gate
Figure 3-6. Timing Requirements for CtrnGate Signal
Table 3-6 shows the minimum pulse width required for the internal signals.
Table 3-6. Minimum Pulse Width for Ctr n Gate Internal Signals
Minimum with
Minimum
RTSI Connector
5 ns
You can select any PFI or RTSI, as well as many other internal signals as
the Counter n Auxiliary (CtrnAux) signal. Much like this CtrnGate signal,
the CtrnAux signal is configured in edge-detection or level-detection mode
depending on the application performed by the counter. The aux signal can
perform many different operations including starting and stopping the
counter, generating interrupts, and saving the counter contents. You can
also use this signal to control the counting direction in edge-counting
applications.
Tgatepw
Tgatepw
5 ns
CtrnGate minimum pulse width
3-12
Description
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