Supermicro X7DBR-3 User Manual page 93

POST Code Description
5Ch Test RAM between 512 and 640 kB
60h Test extended memory
62h Test extended memory address lines
64h Jump to UserPatch1
66h Confi gure advanced cache registers
67h Initialize Multi Processor APIC
68h Enable external and CPU caches
69h Setup System Management Mode (SMM) area
6Ah Display external L2 cache size
6Bh Load custom defaults (optional)
6Ch Display shadow-area message
70h Display error messages
72h Check for confi guration errors
76h Check for keyboard errors
7Ch Set up hardware interrupt vectors
7Dh Initialize Intelligent System Monitoring (optional)
7Eh Initialize coprocessor if present
80h Disable onboard Super I/O ports and IRQs (optional)
81h Late POST device initialization
82h Detect and install external RS232 ports
83h Confi gure non-MCD IDE controllers
84h Detect and install external parallel ports
85h Initialize PC-compatible PnP ISA devices
86h Re-initialize onboard I/O ports.
87h Confi gure Motherboard Confi gurable Devices
(optional)
88h Initialize BIOS Data Area
89h Enable Non-Maskable Interrupts (NMIs)
8Ah Initialize Extended BIOS Data Area
8Bh Test and initialize PS/2 mouse
8Ch Initialize fl oppy controller
8Fh Determine number of ATA drives (optional)
90h Initialize hard-disk controllers
91h Initialize local-bus hard-disk controllers
92h Jump to UserPatch2
93h Build MPTABLE for multi-processor boards
95h Install CD ROM for boot
96h Clear huge ES segment register
97h Fix up Multi Processor table
98h 1-2 Search for option ROMs and shadow if successful. One
long, two short beeps on checksum failure
Appendix B: BIOS POST Codes
B-3