Advanced Chipset Control - Supermicro X7DBR-3 User Manual

X7DBR-3/X7DBR-E User's Manual
Slot#6 PCI-X 133MHz, Slot E1 x8, Slot E2 x4 and Slot E3 x8
Access the submenu for each of the settings above to make changes to the
following:
Option ROM Scan
When enabled, this setting will initialize the device expansion ROM. The options
are Enabled and Disabled.
Enable Master
This setting allows you to enable the selected device as the PCI bus master.
The options are Enabled and Disabled.
Latency Timer
This setting allows you to set the clock rate for Bus Master. A high-priority, high-
throughout device may benefi t from a greater clock rate. The options are Default,
0020h, 0040h, 0060h, 0080h, 00A0h, 00C0h, and 00E0h. For Unix, Novell and
other Operating Systems, please select the option: other. If a drive fails after
the installation of a new software, you might want to change this setting and
try again. A different OS requires a different Bus Master clock rate.
Large Disk Access Mode
This setting determines how large hard drives are to be accessed. The options are
DOS or Other (for Unix, Novelle NetWare and other operating systems).

Advanced Chipset Control

Access the submenu to make changes to the following settings.
*Warning
: Take Caution when changing the Advanced settings. Incorrect
values entered may cause system malfunction. Also, a very high DRAM
frequency or incorrect DRAM timing may cause system instability. When this
occurs, revert to the default setting.
SERR Signal Condition
This setting specifi es the ECC Error conditions that an SERR# is to be asserted.
The options are None, Single Bit, Multiple Bit, and Both.
4GB PCI Hole Granularity
This feature allows you to select the granularity of PCI hole for PCI slots. If MTRRs
are not enough, this option may be used to reduce MTRR occupation. The options
are: 256 MB, 512 MB, 1GB and 2GB.
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