Advertisement
harman/kardon
Figure 9. Write Cycle Polling Flowchart using ACK
First byte of instruction
with RW = 0 already
decoded by the device
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (t
16.
and
Table
To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
NO
Returned
Operation is
NO
Addressing the
Memory
ReSTART
STOP
) is shown in
w
17., but the typical time is shorter.
Figure
9., is:
ACK
YES
Next
YES
Send Address
and Receive ACK
START
NO
Condition
DATA for the
WRITE Operation
Continue the
WRITE Operation
–
Initial condition: a Write cycle is in progress.
–
Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first
byte of the new instruction).
Table
–
Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the
bus master goes back to Step 1. If the device
has terminated the internal Write cycle, it
responds with an Ack, indicating that the
device is ready to receive the second part of
the instruction (the first byte of this instruction
having been sent during Step 1).
AVR 145/230 service manual
M24C64, M24C32
YES
DEVICE SELECT
with RW = 1
Continue the
Random READ Operation
AI01847C
11/26
Page 113 of 135
Advertisement
