Dtv Mb Assy (1/16) - Pioneer PDP-507XC Service Manual

5
3 DDR_DQ[63:0] 3
3 DDR_DQS0
3 DDR_DQS1
3 DDR_DQS2
3 DDR_DQS3
3 DDR_DQS4
3 DDR_DQS5
3 DDR_DQS6
3 DDR_DQS7
3 DDR_DQM0
3 DDR_DQM1
3 DDR_DQM3
3 DDR_DQM2
3 DDR_DQM4
3 DDR_DQM6
3 DDR_DQM5
3 DDR_DQM7
D2.6V_BCM7038
BC1 BC2
0.1uF 0.1uF
DDR_VTT
C311 C312 C313
NI 0805 NI 0805
NI 0805
New DDR routing rules:
------------------------------
All timing is relative the CLK/CLKb that arrive at the destination DDR SDRAM chip.
1) X = CLK/CLKb should be a matched differential pair with a length < 4"
2) Address and control should be X +/- 0.75" (or 100 ps)
3) DQS and DQM should be X +/- 0.75" (or 100 ps)
4) All DQs should match corresponding byte lane DQS/DQMs within +/- 0.20" (or 30 ps)
5) Place 22 ohm resisters on this page near BCM7038.
6) Place 62 ohm resisters for DQ signals midpoint between BCM7038 and DDR SDRAM
7) Place DDR_VREF1/2 resistor dividers near BCM7038
8) Trace impedances need to be 60 ohms +/- 10% (54-66 ohms)
9) Route VREF with 30-mil trace and at least 1 high quality ceramic bypass capacitor
for each connection to a device.
10) All traces should have a >= 3 to 1 spacing ratio fom the reference GND/PWR layer.
(e.g. 15 mil line-to-line spacing for a 5 mil dielectric thickness)
5
6
DDR_ADDR[12:0]
3 DDR_BA1
3 DDR_BA0
3 DDR_CKE
3 DDR_CS0b
3 DDR_RASb
3 DDR_CASb
3 DDR_WEb
3 DDR_CK0
3 DDR_CK0b
3 DDR_CK1
3 DDR_CK1b
C314 C315 C316
NI 0805 NI 0805 NI 0805
6
7
DDR_VTT DDR_VTT
C1
C2
0.1uF
C3
0.01uF
C4
0.1uF
C5
0.01uF
C6
0.1uF
C7
0.01uF
C8
0.1uF
C9
0.01uF
C10
0.1uF
C11
0.01uF
C12
0.1uF
C13
0.01uF
C14
0.1uF
C15
0.01uF
C16
1000pF
C17
0.01uF
C18
1000pF
C19
0.01uF
C429
1000pF
C21
0.01uF
C22
1000pF
C23
0.01uF
C24
1000pF
C25
0.01uF
C26
1000pF
C430
0.01uF
C431
1000pF
C29
470pF
C30
470pF
C31
470pF
C32
470pF
C432
470pF
C433
470pF
470pF
PDP-507XC
7
8

DTV MB ASSY (1/16)

• DDR TERM/CONN BLOCK
8
A
B
C
D
E
F
73