Frequency Generation - Agilent Technologies E8663B Service Manual

Troubleshooting
Overall Description

Frequency Generation

The YIG oscillator generates frequencies from 3.2 to 10 GHz.
Output Oscillator
Frequency Frequency
< 250 MHz 3.2 to 10 GHz
250 MHz
to 4 to 8 GHz
3.2 GHz
> 3.2 GHz 3.2 to 10 GHz
Highband Path – Frequencies 3.2 GHz and Above
The output of the YIG oscillator (>3.2 GHz) is routed to the A29 20 GHz Doubler microcircuit. The signal is routed
through a bypass circuit, then the signal is amplified and filtered.
The A29 20 GHz Doubler output is routed to the A30 Modulation Filter. The A30 contains amplitude and pulse
modulators, amplifiers, and filters.
The output of the A30 Modulation Filter is routed to the A24 Highband Coupler and A25 Highband Detector, then
through the AT1 attenuator to the front panel RF output connector.
Lowband Path – Frequencies Below 3.2 GHz
The YIG oscillator output is tuned between 4 and 8 GHz. The YIG oscillator output is routed to the A29 20 GHz
Doubler microcircuit, where a portion of the signal is coupled off and routed to the A6 Frac–N. A divider on the
A6 Frac–N divides the 4 to 8 GHz signal to a frequency between 250 MHz and 3.2 GHz. This signal is then routed to
the A8 Output assembly where it is amplified, filtered and modulated.
Frequencies below 250 MHz are generated on the A8 Output by mixing the output signal from the A6 Frac–N (between
1000 and 750 MHz) with a 1 GHz LO from the A7 Reference.
The 100 kHz to 3.2 GHz signal is routed to the A23 Lowband Coupler/Detector, and then switched to the
A25 Highband Coupler/Detector by a switch in the A30 Modulation Filter microcircuit, then to the attenuator and RF
output connector.
Frequency Control
CW Mode
The A9 YIG Driver, A18 CPU, A7 Reference, A5 Sampler, and A6 Frac–N establish frequency accuracy and stability.
This circuitry is commonly referred to as a phase lock loop (PLL).
In CW operation, the A18 CPU programs the A9 YIG Driver pre–tune DAC to output a voltage that coarsely tunes the
YIG oscillator to the desired frequency. The A18 CPU also sets the A6 Frac–N VCO and the A5 Sampler phase dividers
and VCO to a frequencies such that when the A6 Frac–N, A5 Sampler signal, and the YIG oscillator signals are in
phase, the output of the phase comparator is 0 volts, and the phase lock loop is at the desired output frequency.
When the phases of these two signals (YO feedback and reference) are not the same (in phase), the output of the
phase detector changes to some voltage other than 0 volts.
The phase detector output is then integrated (the integrator voltage is proportional to the frequency error), and
routed to the A9 YIG Driver where it is summed with the pre–tune DAC voltage, causing the YIG's output frequency
to change. Once the phase of the two signals matches, the phase detector output voltage returns to 0 volts, and the
integrator maintains a constant output voltage, holding the YIG output frequency constant.
To perform a phase comparison between the A6 Reference signal and the RF signal coupled off by the A20 Doubler, a
sampling function on the A5 Sampler converts the RF (in GHz) to an IF frequency in the MHz range. A 10 MHz signal
from the A7 Reference Assembly is used as the reference to the A6 Frac–N VCO (Voltage Controlled Oscillator) to
maintain the A6 Frac–N frequency accuracy. The frequency reference for the A7 Reference can be an:
• external 10 MHz signal
• internal high stability 10 MHz OCXO (Oven Controlled Crystal Oscillator) and the A7 Reference
1-50
Path
A6 Frac–N signal is mixed with a 1 GHz signal on the A8 output
assembly;
Lowband path, the difference is used to generate the lower frequencies.
and part of
highband path
Oscillator output is divided by 2/4/8/16 on the A6 Frac–N assembly.
Highband path
Notes
Agilent E8663B Analog Signal Generator Service Guide