Pci-E Slot Breakdown - EVGA X299 FTW-K User Manual

EVGA X299 FTW - K (142-SX-E297)

PCI-E Slot Breakdown

PCI-E Lane Distribution (44 Lane SKX CPU's)
PE1 – x4 (Gen3, x4 lanes from PCH)
PE2 – x16 (Gen3, x16 lanes from CPU, x8 shared with PE3)
PE3 – x16 (Gen3, x8 lanes from CPU, shares 8 of PE2's 16 lanes)
PE4 – x16 (Gen3, x8 lanes from CPU, shares 8 of PE5's 16 lanes)
PE5 – x16 (Gen3, x16 lanes from CPU, x8 shared with PE4)
PE6 – x1 (Gen3, x1 lane from PCH)
PCI-E Lane Distribution (28 Lane SKX CPU's)
PE1 – x4 (Gen3, x4 lanes from PCH)
PE2 – x16 (Gen3, x16 lanes from CPU, x8 shared with PE3)
PE3 – x16 (Gen3, x8 lanes from CPU, shares 8 of PE2's 16 lanes)
PE4 – x16 (Not functional with a 28 lane processor.)
PE5 – x16 (Gen3, x8 lanes from CPU)
PE6 – x1 (Gen3, x1 lane from PCH)
PCI-E Lane Distribution (16 Lane KBX CPU's)
PE1 – x4 (Gen3, x4 lanes from PCH)
PE2 – x16 (Gen3, x8 lanes from CPU)
PE3 – x16 (Not functional with a 16 lane processor.)
PE4 – x16 (Not functional with a 16 lane processor.)
PE5 – x16 (Gen3, x8 lanes from CPU, disabled if 110mm M.2 is used)
PE6 – x1 (Gen3, x1 lane from PCH)
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