National Instruments 622 Series User Manual page 256

Appendix B Timing Diagrams
PFI, RTSI,
or PXI_STAR
Other Internal
Signals
80 MHz Timebase
20 MHz Timebase
100 kHz Timebase
PXICLK10
Pin to Internal Signal Delays
Input timing is the timing specification for importing a signal to an internal bus on the M Series
device. Table B-26 shows the input timing for the counters on all input terminals. Signals refer
to the signal at the I/O connector of the device, and signals appended with _i refer to the signal
internal to the device after the input buffer.
Figure B-42. Pin to Internal Signal Delays Timing Diagram
or PXI_STAR
PFI_i, RTSI_i,
or PXI_STAR_i
Time From
*
t PFI
1
RTSI
STAR
*
The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the
trigger group for a given condition (maximum or minimum timing). This difference can be useful when
two external signals will be used together and the relative timing between the signals is important.
B-32 | ni.com
Figure B-41. Counter/Timer Circuitry
PFI_i, RTSI_i,
or PXI_STAR_i
Selected_Gate
Gate
Logic
Selected_Source
PFI, RTSI,
Table B-26. Pin to Internal Signal Delays Timing
To
PFI_i
RTSI_i
STAR_i
Count_Enable
32-Bit
Counter
t
t
1
1
Min (ns)
5.2 6.2
2.0 2.5
0.9 —
PFI, RTSI,
or PXI_STAR
(Counter n Gate)
Out_o
PFI, RTSI,
or PXI_STAR
(Counter n
Internal Output)
PFI, RTSI,
or PXI_STAR
(Counter n Source)
Max (ns)
18.2 22.0
5.0 6.0
— 2.5