Sony DVP-NS3100ES Service Manual page 70

DVP-NS3100ES
MAIN BOARD IC404 uPD70F3259YGF-41A-JBT-A (SYSTEM CONTROLLER)
Pin No. Pin Name
1 KEY1
2 KEY0
3 AVDD
4 AVSS
5, 6 NC
7 AVREF
8 232C_RTS
9 232C_CTS
10 FLMD0
11 VDD
12 REGC
13 VSS
14 XTI
15 XTO
16 RESET
17 SUB_CLK_IN
18 SUB_CLK_OUT
19 NC
20 KEY_INT
21 232C_INT
22 DEBUGRST
23 BE_CS
24 CLKG_SDA
25 CLKG_SCL
26 NC
27 232COUT
28 232CIN
29 232CPW_DOWN
30 NC
31 SIRCS
32 HDMI_RST
33 BE_BUSY
34 BE_RST
35 EVSS
36 EVDD
37 ILINK_TX
38 ILINK_RX
39 TEST_MODE_IN
40 SPDIF_SW
41 FS_SEL
42 CLK_SW
43 ILINK_RST
44 ILINK_OSC_SW
45 BE_TXD
46 BE_RXD
47 LED_PLAY
70
I/O
I Front panel keys input terminal (A/D input)
I Key input terminal Not used
- Power supply terminal (+3.3V)
- Ground terminal
O Not used
I Reference voltage (+3.3V) input terminal
O Transmit request signal output terminal for the RS232C Not used
I Transmit request signal input terminal for the RS232C Not used
I Flash memory data write mode control signal input terminal
- Power supply terminal (+3.3V)
O Connection terminal to the regulator capacitor
- Ground terminal
I Main system clock input terminal (5 MHz)
O Main system clock output terminal (5 MHz)
System reset signal input from the reset signal generator "L": reset For several
I
hundreds msec. after the power supply rises, "L" is input, then it change to "H"
I Sub system clock input terminal Not used
O Sub system clock output terminal Not used
O Not used
I Wake up signal input from front panel keys or remote commander
I Wake up signal input terminal for the RS232C Not used
O Reset signal output terminal Not used
O Chip select signal output to the CPU
I/O I2C two-way data bus terminal for the clock generator Not used
I/O I2C bus clock signal input/output terminal for the clock generator Not used
O Not used
O Serial data output terminal for the RS232C Not used
I Serial data input terminal for the RS232C Not used
I RS232C power down signal output terminal for the RS232C Not used
O Not used
Remote control signal input from the remote control receiver and CONTROL S IN/IR
I
IN jack
O HDMI reset signal output terminal Not used
I Busy signal input from the CPU
O Reset signal output to the flash memories, CPU and lip sync adjust "L": reset
- Ground terminal
- Power supply terminal (+3.3V)
O UART transmit data output terminal for the i.link Not used
I UART receive data input terminal for the i.link Not used
Test mode on/off control signal input terminal "L": normal mode,
I
"H": test modeFixed at "L" in this set
O Digital out on/off control signal output terminal "H": digital out on
O Sampling frequency selection signal output to the clock generator
O Audio clock selection signal output terminal Not used
O Reset signal output terminal for the i.link Not used
O I.link OSC on/off control signal output terminal Not used
O UART transmit data output to the CPU
I UART receive data input from the CPU
O LED drive signal output terminal for playback indicator Not used
Description