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PGA411-Q1
SLASE76E – NOVEMBER 2015 – REVISED AUGUST 2017
5 Pin Configuration and Functions
OUTA
1
OUTB
2
ECLKSEL
3
VCCSW
4
BMODE0
5
VSW
6
NC
7
PGND
8
ORS
9
VEXTS
10
TEST
11
NRESET
12
INHB
13
FAULTRES
14
PRD
15
FAULT
16
NC - No internal connection
PIN
TYPE
NAME
NO.
AMODE
28
AOUT
30
BMODE0
5
COMAFE
35
DGND
21
ECLKSEL
3
FAULT
16
FAULTRES
14
IE1
34
IE2
33
INHB
13
(1) I = input; O = output; I/O = input and output; P = power
4
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64-Pin HTQFP With Exposed Thermal Pad
Pin Functions
LOGIC
(1)
INPUT OR
OUTPUT
I
Input
Accelerated mode select
ORD (angle and velocity) analog output. Use for testing only, in production connect to
O
—
ground.
I
Input
Resolution select, input low is 10-bit mode, input high is 12-bit mode
O
—
Common-mode output for the analog front-end (AFE)
P
—
Digital ground
I
Input
Clock select input
O
Output
Fault-detection signal output (open-drain structure)
I
Input
Fault reset input (faults are reset when this pin is LOW)
I
—
Positive input to the AFE from the resolver exciter coil
I
—
Negative input to the AFE from the resolver exciter coil
I
Input
Inhibit function and output data hold
Product Folder Links:
PAP Package
Top View
Thermal
Pad
DESCRIPTION
Copyright © 2015–2017, Texas Instruments Incorporated
PGA411-Q1
www.ti.com
48
ORD9
47
ORD10
46
ORD11
45
ORD12
44
ORDCLK
43
OSIN
42
IZ4
41
IZ2
40
QGND
39
QVCC
38
IZ1
37
IZ3
36
OCOS
35
COMAFE
34
IE1
33
IE2
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