Icom IC-R9500 Service Manual Addendum page 246

MAIN CPU2 (LOGIC/LOGIC-A UNIT; IC604)
Pin Port
number name
5–9 H8_A0–
A4,
11–17 H8_A5–A11, Output address bus signals.
19, 20 H8–A12, A13,
Input port for hte PLL unlock signal
21 UNLKA
from the PLL unit.
Input port for hte PLL unlock signal
22 UNLKB
from the PLL unit.
23 ECK Outputs clock signal to the EEPROM.
I/O port for the data signal from/to the
24 EDT
EEPROM.
Outputs clock signal to the EEPROM
26 DSCLA
on the RF-Aunit.
I/O port for the data signal from/to the
EEPROM on the LOGIC/LOGIC-A
27 DSDAA
UNIT.
Outputs clock signal to the EEPROM
28 DSCLB
on the LOGIC/LOGIC-A UNIT.
I/O port for the data signal from/to the
29 DSDAB
EEPROM on the LOGIC/LOGIC-A
UNIT.
30 RTKI Input port for the RTTY keying signal.
Input port for the transverter control
31 TRVI
signal from ACC jack on the rear panel.
Outputs data signals to the DDS, PLL
33 SDAT
and DSPICs on the SCOPE/TV/TV unit.
Outputs strobe signal to the PLL IC on
34 SST2
the SCOPE/TV unit.
Outputs external SEND relay (lead
type) control signal.
35 EXRL1
High : The relay switches ON.
Outputs external SEND relay (semi-
conductor type) control signal.
36 EXRL2
High : The relay switches ON.
42 PCK/CON0 Outputs clock signal to the PLL ICs.
PDAT/CON1 Outputs data signal to the PLL ICs.
43
Outputs strobe select signal to the
46 PSLA
PLL ICs.
47 PSTA Outputs strobe signal to the PLL ICs.
Outputs strobe select signal to the
48 PSLB
PLL IC.
Outputs strobe signal to the PLL IC.
49 PSTB
Outputs clock signal to the ICs (other
51 MCK
than PLL, SCOPE/TV and DSP ICs).
Outputs data signal to the ICs (other
52 MDAT
than PLL, SCOPE/TV and DSP ICs).
54 CTXD Output port for the CI-V data.
Input port for the CI-V data and CI-V
55
CRXD/CBSY
bus busy signals.
Description
Pin Port
number name
56 DSPCK
57 DSPR
58 ISTA
59 SST1
60 SPS0
61 SCK
63–69, 71, H8_D0–
73–80 H8_D15
81 MUTI
83 NSQA
104 OCK
105 ODAT
106 OCS
107 OSS1
108 OSS2
109 FRWT
110 DULS
113 LPLVL
114 HPLV
115 2PLV
116 3PLV
CMETL Input port for the VD meter control signal.
117
118 UNLK
138 SDSPCK
140 DFRS
142 SDSPR
3 - 7
Description
Outputs clock signal to the DSP IC.
Outputs data signal to the DSP IC.
Outputs start signal to the internal
antenna tuner.
Outputs chip select signal to the DDS
IC on the SCOPE/TV unit.
Outputs profile select signal to the
DDS IC on the SCOPE/TV unit.
Outputs clock signals to the DDS, PLL
and DSP ICs on the SCOPE/TV unit.
I/O port for data bus signals.
Input port for the external mute control
signal.
High : Mute ON.
Input port for the noise pulse signal
from the MAIN unit.
Input port for the noise pulse signal
from the MAIN unit.
Outputs serial data to the OSC unit.
(Commonly used for DDS)
Outputs chip select signal to the OSC
unit.
Outputs REFcontrol signal to the OSC
unit.
High : Outputs reference signal.
Outputs REF select signal to the OSC
unit.
High : External reference signal.
Outputs farm-up control signal.
Low : Output control signal.
Outputs AF mute control signal to the
RX circuit.
Low : Squelch is open.
Input port for the "FOR" signal.
Input port for the "REF" signal.
Input port for 2nd LO signal.
( for monitoring.)
Input port for 3rd LO signal.
( for monitoring.)
Input port for PLL unlock signal from
PL IC.
Outputs clock signal to the D/A con-
verter (IC603).
Outputs serial data signal for command
data.
Outputs clock signal for command data.