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7. Digital filter selection:
Digital low-pass filters are essential to the functionality of a delta-sigma ADC, which relies on
oversampling and noise shaping to push quantization noise out of band. There are a variety of options
for digital filters available in the ADS125H02 device. When choosing a digital filter, consider the
following tradeoffs:
•
Slower data rates (higher oversampling ratios) have lower noise bandwidth. They are great for
noise, but not for data throughput or detection of transient events.
•
The built-in PGA monitors are able to assist in detecting transient events that may affect the
conversion results; therefore, the digital filter is generally able to be run at a slower data rate for
better noise performance.
•
Higher-order SINC filters have slower settlings times when an input step is applied, but they provide
lower noise bandwidth and increased notch width for removing common noise signals, such as
power line noise which in practice may not occur at exactly 50Hz or 60Hz.
•
Digital filter notches occur at intervals of the SINCx filter data rate, so data rates of 50 SPS, 60 SPS
or less are recommended for attenuating power line noise.
•
The 20 SPS FIR filter is unique from the SINCx filters in that it provides simultaneous rejection of
50- and 60-Hz noise and also settles within a single conversion cycle (like the SINC1 filter).
In this application, TI recommends a low-latency 20 SPS using a SINC1 filter, which is shown in the
pseudocode example in the following section.
For more information about digital filters in the ADS125H02 device, see the following:
•
The Digital Filter section of the
•
Digital Filter Types in Delta-Sigma ADCs Application Report
Register Settings
Register
Register
Address
Name
05h
MODE3
MODE2
MODE4
10h
MODE4
10h
MODE4
02h
MODE0
02h
MODE0
SBAA386 – December 2019
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ADS125H02 Data Sheet
Configuration Register Settings for Voltage and Current Inputs
Field
Register Value
GPIO_DAT[3:0]
See
MUX509 Truth Table and
GPIO_DAT Configuration
GPIO_DIR[3:0]
GPIO_CON[3:0]
MUX[2:0]
GAIN[3:0]
DR[4:0]
FILTER[2:0]
Four-channel, differential input, DAQ front-end circuit with configurable
Copyright © 2019, Texas Instruments Incorporated
Description
GPIO state (to control the external MUX)
1000
GPIO[2:0] outputs, GPIO[3] input
0111
GPI0[2:0] connected GPIO[3] disconnected
000
Internal MUX
0010 or 0011
PGA - Gains for voltage and current
measurements, respectively
00100
Data rate: 20 SPS
000
Digital filter: SINC1
voltage and current inputs
5
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