Serial Peripheral Interface (Spi) - Motorola CDM Series Detailed Service Manual

Section 3: 1-6
synthesizer is changed in small amounts if there is a possibility of harmonics of the clock source
interfering with the desired radio receive frequency.
The ASFIC CMP synthesizer loop uses C0245, C0246 and R0241 to set the switching time and jitter
of the clock output. If the synthesizer cannot generate the required clock frequency it will switch
back to its default 3.6864 MHz output.
Because the ASFIC CMP synthesizer and the µP system will not operate without the 16.8 MHz
reference clock it (and the voltage regulators) should be checked first when debugging the system.
The µP uses XTAL Y0131 and associated components to form a Real Time Clock (RTC). It may be
used to display the time on control heads with display or as time stamp for incoming calls or
messages. The real time clock is powered from the voltage VSTBY to keep it running while the radio
is switched off. When the radio is disconnected from its supply voltage, the time must be set again.
1.9

Serial Peripheral Interface (SPI)

The µP communicates to many of the ICs through its SPI port. This port consists of SPI TRANSMIT
DATA (MOSI) (U0101-100), SPI RECEIVE DATA (MISO) (U0101-99), SPI CLK (U0101-1) and chip
select lines going to the various ICs, connected on the SPI PORT (BUS). This BUS is a
synchronous bus, in that the timing clock signal CLK is sent while SPI data (SPI TRANSMIT DATA
or SPI RECEIVE DATA) is sent. Therefore, whenever there is activity on either SPI TRANSMIT
DATA or SPI RECEIVE DATA there should be a uniform signal on CLK. The SPI TRANSMIT DATA
is used to send serial from a µP to a device, and SPI RECEIVE DATA is used to send data from a
device to a µP.
On the controller there are two ICs on the SPI BUS, ASFIC CMP (U0221-22), and EEPROM
(U0111-5). In the RF sections there are 2 ICs on the SPI BUS, the FRAC-N Synthesizer, and the
Power Control IC (PCIC). The SPI TRANSMIT DATA and CLK lines going to the RF section are
filtered by L0481 / R0481 and L0482 / R0482 to minimize noise. The chip select line CSX from
U0101 pin 2 is shared by the ASFIC CMP, FRAC-N Synthesizer and PCIC. Each of these ICs check
the SPI data and when the sent address information matches the IC's address, the following data is
processed. The chip select lines for the EEPROM (EE CS), Voice Storage (VS CS), expansion
board (EXP1 CS, EXP2 CS) and option board (OPT CS) are decoded by the address decoder
U0141.
When the µP needs to program any of these ICs it brings the chip select line CSX to a logic "0" and
then sends the proper data and clock signals. The amount of data sent to the various ICs are
different; e.g., the ASFIC CMP can receive up to 19 bytes (152 bits) while the PCIC can receive up
to 6 bytes (48 bits). After the data has been sent the chip select line is returned to logic "1".
The option board interfaces are different in that the µP can also read data back from devices
connected.The timing and operation of this interface is specific to the option connected, but
generally follows the pattern:
1. an option board device generates a service request via J0551-29, line RDY and µP pin 79,
2. the main board asserts a chip select for that option board device via U0141-14, line OPT CS,
J0551-30,
3. the main board µP generates the CLK (J0551-3),
4. the main board µP writes serial data via J0551-15 and reads serial data via J0551-16 and,
5. when data transfer is complete the main board terminates the chip select and CLK activity.
Section : 6881091C63-F
Controller Circuits