Denon HEOS AVR Service Manual page 35

PIN
5-V
NO. NAME I/O
TOLERANT
19 BCK O No Main output port, Bit clock output
20 SCKO O No Main output port, System clock output
21 DGND – – Ground, for digital
22 DVDD – – Power supply, 3.3 V (typ.), for digital
Software control I/F, SPI data output / I2C slave address set-
23 MDO/ADR0 I/O Yes
ting0(2)
24 MDI/SDA I/O Yes Software control I/F, SPI data input / I2C data input/output(2) (3)
25 MC/SCL I Yes Software control I/F, SPI clock input / I2C clock input(2)
Software control I/F, SPI chip select / I2C slave address set-
26 MS/ADR1 I Yes
ting1(2)
Control mode setting, (see the Serial Control Mode section,
27 MODE I No
Control Mode Pin Setting)
28 RXIN7/ADIN0 I Yes Biphase signal, input 7 / AUXIN0, serial audio data input(2)
29 RXIN6/ALRCKI0 I Yes Biphase signal, input 6 / AUXIN0, LR clock input(2)
30 RXIN5/ABCKI0 I Yes Biphase signal, input 5 / AUXIN0, bit clock input(2)
31 RXIN4/ASCKI0 I Yes Biphase signal, input 4 / AUXIN0, system clock input(2)
32 RXIN3 I Yes Biphase signal, input 3(2)
33 RXIN2 I Yes Biphase signal, input 2(2)
34 RST I Yes Reset Input, active low(2) (4)
35 RXIN1 I Yes Biphase signal, input 1, built-in coaxial amplifier
36 VDDRX – – Power supply, 3.3 V (typ.), for RXIN0 and RXIN1.
37 RXIN0 I Yes Biphase signal, input 0, built-in coaxial amplifier
38 GNDRX - - Ground, for RXIN
Oscillation circuit input for crystal resonator or external XTI
39 XTI I No
clock source input(5)
40 XTO O No Oscillation circuit output for crystal resonator
41 AGND – – Ground, for PLL analog
42 VCC – – Power supply, 3.3 V (typ.), for PLL analog
External PLL loop filter connection terminal; must connect rec-
43 FILT O No
ommended filter
ADC common voltage output; must connect external decou-
44 VCOM O No
pling capacitor
45 AGNDAD – – Ground, for ADC analog
46 VCCAD – – Power supply, 5.0 V (typ.), for ADC analog
47 VINL I No ADC analog voltage input, left channel
48 VINR I No ADC analog voltage input, right channel
(1) Schmitt trigger input
(2) Schmitt trigger input
(3) Open-drain configuration in I2C mode
(4) Onboard pull-down resistor (50 k Ω , typical)
(5) CMOS Schmitt trigger input
BLOCK DIAGRAM
DESCRIPTION
35
FILT
AUXIN 0
AUTO
RXIN7
DIR
RXIN 0 RXIN0 DIR
DOUT
RXIN 1 RXIN1 ADC
PLL
RXIN 2 RXIN2 AUXIN0
SCKO/ BCK/LRCK
RXIN 3 RXIN3 AUXIN1
RXIN 4/ASCKI 0 RXIN4 Lock :DIR AUXIN2
Unlock:ADC
RXIN 5/ABCKI 0 RXIN5 Clock/ Data
Recovery
RXIN 6/ALRCKI 0 RXIN6
RXIN 7/ADIN0 RXIN7 AUTO
DIR
MPIO_ A0
RXIN8 ADC
Lock Detection
MPIO_ A1
RXIN9 AUXIN0
MPIO_ A
MPIO_ A2
RXIN10 AUXIN1
SELECTOR
MPIO_ A3
RXIN11 RECOUT 0 AUXIN2
DITOUT RECOUT 1
RECOUT0
RECOUT1
ADC
DITOUT
VINL
ADC Mode
ADC
VINR Control
VCOM
Com. Supply
AUTO
MPIO _C0
DIR
ADC Standalone
MPIO _C1 ADC
MPIO_ C AUXOUT
MPIO _C2 AUXIN0
SELECTOR
AUXIN1 AUXIN 2
MPIO _C3
AUXIN1
ADC Clock
(SCK /BCK/LRCK)
Divider
XTI
XTO OSC
XMCKO
Secondary BCK / LRCK
(To MPIO _A & MPO0/1 )
XMCKO
Divider
Divider
Selector
REGISTER EXTRA DIR FUNCTIONS
MC /SCL
DIR DIR
MDI /SDA Function DIR CS ERROR DETECTION
2 P and P f Calculator
SPI/I C Control ( 48-bit)
C D S Non-PCM DETECTION
MDO /ADR 0 INTERFACE
f Calculator
S
MS/ADR 1
GPIO/GPO DIT CS All Port Flags
DIR Interrupt
Data ( 48-bit) f Calculator
S
DTS-CD/LD Detection
Validity Flag
User Data
POWER SUPPLY
RST Channel Status Data
Reset
BFRAME Detection
and Mode ADC DIR DIR
MODE
ALL
Set Interrupt System
ANALOG ANALOG ANALOG
VCCAD AGNDAD VCC AGND VDDRX GNDRX DVDD DGND
SCKO
MAIN BCK
OUTPUT
LRCK
PORT
DOUT
DIT
MPO 0
MPO0/1
MPO 1
SELECTOR
MPIO_B0
MPIO_B1
MPIO _B
MPIO_B2
SELECTOR
MPIO_B3
SBCK /SLRCK
( to MPIO_A )
ERROR /INT0
NPCM /INT1
MPIO_ A
MPIO_ B
MPIO_ C
MPO0
MPO1