Denon HEOS AVR Service Manual page 32

SEMICONDUCTORS
Only major semiconductors are shown, general semiconductors etc. are omitted to list.
The semiconductor which described a detailed drawing in a schematic diagram are omitted to list.
1. IC's
R5F5634BCDFB (DIGITAL : IC301)
PE2
109
PE1 110
PE0 111
P64 112
P63 113
P62
114
P61 115
PK3 116
P60 117
PK2 118
PD7 119
PD6 120
PD5 121
PD4 122
PD3 123
PD2 124
PD1 125
PD0
126
P93 127
P92 128
P91 129
VSS 130
P90
131
VCC
132
P47 133
P46 134
P45 135
P44 136
P43
137
P42 138
P41 139
VREFL0 140
P40 141
VREFH0 142
AVCC0
143
P07
144
Note: This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table
"List of Pins and Pin Functions (144-Pin LQFP)".
Note 1. The P73 pin is available only in 5-V packages. It is not available in 3-V packages.
Note 2. The PL5 pin is available only in 3-V packages. It is not available in 5-V packages.
Terminal Functions
Pin Pin Name Signal Name
1 AVSS AVSS AVSS
2 P05/DA1 (DAC Output)
3 VREFH VREFH DAC VCC
4 P03/DA0 BDOWN AC cut off DET (INT)
5 VREFL VREFL DACGND
6 P02/IRQ10 CEC_IN Regacy CEC input
7 P01/PMC1 REMOTE Wired IR Remote Receiver
8 P00/PMC0 IRSIG1_MCU IR Remote Receiver
9 PF5/IRQ4 IRSIG2_MCU IR Remote Receiver
10 EMLE EMLE JTAG Emurator Enable
11 PJ5 NET_PW Network standby power switch
12 VSS
13 PJ3/RTS0# FRONT_BLUE_LED FRONT BLUE LED Drive (Need DIMMER control PWM)
14 VCL VCL 0.1 μ F capacitor to VSS
15 PJ1 CEC_OUT Regacy CEC output
16 MD/FINED MD/FINED MODE to JTAG
17 PJ2 HDMI_PW HDMI_Power supply switch
18 PJ4 DSP_PW DSP_Power supply switch
19 RES# MCU_RESET Reset
20 XTAL XTAL Crystal
21 VSS
22 EXTAL EXTAL Crystal
23 VCC
24 P35/NMI (NA)
25 TRST# TRST# JTAG Emurator TRST
26 P33/RXD0 USBCNVRxD UART for MCP2200/FT232R
27 P32/TXD0 USBCNVTxD UART for MCP2200/FT232R
28 TMS TMS JTAG Emurator TMS
29 TDI TDI JTAG Emurator TDI
30 FINEC/TCK FINEC/TCK JTAG Emurator TCK
31 TDO TDO JTAG Emurator TDO
32 P25 BD3473_CL CL for BD3473KS2
33 P24/SCK3 DSPARESET DSPA reset
34 P23/CTS0# BD3473_DATA DATA for BD3473KS2
72 P74
71 P75
70 PC2
69 P76
68 P77
PC3
67
PC4
66
P80
65
64 P81
63 P82
62 PC5
PC6
61
60 PC7
59 VCC
RX634 Group 58 P83
57 VSS
PLQP0144KA-A 56 P50
P51
55
(144-pin LQFP)
54 P52
53 P53
(Top view)
52 P54
51 P55
P56
50
PH0
49
48 PH1
47 PH2
46 PH3
45 P12
P13
44
P14
43
42 P15
41 P86
40 P16
39 P87
P17
38
P20
37
Signal function I/O
-
AO
-
AO
-
I
I
I
I
I
O
-
O
-
O
I
O
O
I
O
-
I
-
I
I
I
O
I
I
I
O
O
O
O
35 P22/SCK0 CEC_PW
36 P21/SCL1 I2C3_SCL
37 P20/SDA1 I2C3_SDA
38 P17/TXD3 VOL+
39 P87 NOM_PW
40 P16/RXD3 VOL-
41 P86 OBUF_ZSTBY
42 P15/TCLKB DETON_COAX
43 P14/TCLKA DETON_OPT
44 SDA0 HSDA0
45 SCL0 HSCL0
46 PH3 RX3_DET
47 PH2 RX2_DET
48 PH1 RX1_DET
49 PH0/CACREF RX0_DET
50 P56 OR_SDAC_INSEL2
51 P55 OR_SDAC_INSEL1
52 P54/RTS2# OR_SDAC_INSEL0
53 P53 PLD-SPILT
Pu/Pd STBY
54 P52/RXD2 PLD-SPICLK
- -
55 P51/SCK2 PLD-SPIDATA
56 P50/TXD2 CMWAKEUP
- -
57 VSS
58 P83 MDAC_MUTE
- -
59 VCC
I
60 PC7 UBOOTEN
I
61 PC6 HPD-MCU0
I
62 PC5 HPD-MCU1
I
63 P82 DIRRESET
10KPD I
64 P81 PVDD_HL_SW
L
65 P80
- -
66 PC4/SCK5 HPD-MCU2
O
67 PC3/TXD5 HPD-MCU3
- -
68 P77/TXD11 PLD-TDI
O
69 P76/RXD11 PLD-TDO
I
70 PC2/RXD5 TX0_HPD
O
71 P75/SCK11 PLD-TCK
L
72 P74 PLD-TMS
4.7KPU I
73 PC1/SDA3 CPU_EEPROM_SDA
- O
74 PL1 DIST_MUTE
- -
75 PC0/SCL3 CPU_EEPROM_SCL
- I
76 PL0 STBY_STATUS
- -
77 PL5/CECIO CEC
4.7KPU I
78 PB7/TXD9 CM_RxD
4.7KPD I
79 PB6/RXD9 CM_TxD
I
80 PB5/SCK9 UARTSCKIN
O
81 PB4/RTS9# CM_CTS
4.7KPU I
82 PB3 OR_DSPAI_SL2
4.7KPU I
83 PB2 OR_DSPAI_SL1
4.7KPU I
84 PB1 OR_DSPAI_SL0
4.7KPU O
85 P72 CLIP_OTW -> FAULT
O
86 P71 DSPA_HOLD
L
87 PB0 DETON_COAX
O
32
CEC Power supply switch
I2C-I/F for PCM9211, BMA250
I2C-I/F for PCM9211, BMA250
Master Volume rotation DET VOL+
NORMAL Power
Master Volume rotation DET VOL-
Set PLD into Stand-by
AUTO ON COAX
AUTO ON OPT
I2C-I/F for HDMI(NM864788A)
I2C-I/F for HDMI(NM864788A)
HDMI IN 5V detect
HDMI IN 5V detect
HDMI IN 5V detect
HDMI IN 5V detect
OR_SDAC_INSEL2(PLD)
OR_SDAC_INSEL1(PLD)
OR_SDAC_INSEL0(PLD)
PLD Mute serial control
PLD Mute serial control
PLD Mute serial control
Core Module Wake-up
MUTE SDATA of Main DAC(PLD)
User Boot Mode Enable
HDMI HPD assert
HDMI HPD assert
RESET DIR
D-AMP PVDD Higjh/Low SW
HDMI HPD assert
HDMI HPD assert
PLD-TDI
PLD-TDO
Sens TX0 HPD
PLD-TCK
PLD-TMS
CPU_EEPROM_SDA
DIST_MUTE
CPU_EEPROM_SCL
STBY_STATUS
CEC-I/O
UART for LEGO
UART for LEGO
7.5MHz(8x921.6k) UART Clock Input
UART for LEGO
OR_DSPA_INSEL2(PLD)
OR_DSPA_INSEL1(PLD)
OR_DSPA_INSEL0(PLD)
Shutdown signal from TPA3251D2
DSPA_HOLD
AUTO ON COAX
O O
I/O 4.7KPU I
I/O 4.7KPU I
I I
O L
I I
O O
I I
I I
I/O 10KPU I
I/O 10KPU I
I I
I I
I I
I I
O O
O O
O O
O (PU) O
O O
O O
O 4.7KPD L
- - -
O H
- - -
I 4.7KPU I
O O
O O
O L
O L
O L
O O
O O
Z/O Z
Z/O Z
I I
Z/O Z
Z/O Z
I I
O L
I/O 10KPU I
I I
I/O Ext-PU I
I I
O L
I I
O L
O O
O O
O O
I 10KPU I
O L
I I