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6 I/O PORTS (PPORT)
Px Port interrupt Flag Register
Register name
Bit
PxINTF
15–8 –
7–0 PxIF[7:0]
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 Reserved
Bits 7–0
PxiF[7:0]
These bits indicate the port input interrupt cause occurrence status.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag
0 (W):
Ineffective
Px Port interrupt Control Register
Register name
Bit
PxINTCTL
15–8 PxEDGE[7:0]
7–0 PxIE[7:0]
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 PxeDGe[7:0]
These bits select the input signal edge to generate a port input interrupt.
1 (R/W): An interrupt will occur at a falling edge.
0 (R/W): An interrupt will occur at a rising edge.
Bits 7–0
Pxie[7:0]
These bits enable port input interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Note: To prevent generating unnecessary interrupts, clear the corresponding interrupt flag before en-
abling interrupts.
Px Port Chattering Filter enable Register
Register name
Bit
PxCHATEN
15–8 –
7–0 PxCHATEN[7:0]
*1: The bit configuration differs depending on the port group.
Bits 15–8 Reserved
Bits 7–0
PxChaTen[7:0]
These bits enable/disable the chattering filter function.
1 (R/W): Enable (The chattering filter is used.)
0 (R/W): Disable (The chattering filter is bypassed.)
Px Port Mode Select Register
Register name
Bit
PxMODSEL
15–8 –
7–0 PxSEL[7:0]
*1: The bit configuration differs depending on the port group.
*2: The initial value may be changed by the port.
Bits 15–8 Reserved
6-8
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x00
Seiko epson Corporation
Reset
R/W
–
R
–
H0
R/W
Cleared by writing 1.
Reset
R/W
H0
R/W
–
H0
R/W
Reset
R/W
–
R
–
H0
R/W
Reset
R/W
–
R
–
H0
R/W
S1C17F13 TeChniCal Manual
Remarks
Remarks
Remarks
Remarks
(Rev. 1.0)
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