Block Ram Generation And Capture - Xilinx Zynq UltraScale+ RFSoC ZCU208 User Manual

DAC_DMA_DDR
M_AXIS_03
M_AXIS_10
M_AXIS_11
M_AXIS_12
M_AXIS_00
M_AXIS_01
M_AXIS_02
M_AXIS_13
GPIO_DDR_SWITCH
Dout[0:0]
Dout1[0:0]
Dout2[0:0]
Dout3[0:0]
Dout4[0:0]
Dout5[0:0]
Dout6[0:0]
Dout7[0:0]

Block RAM Generation and Capture

The block RAM generation and capture are described in the "RF Analyzer" section in the Zynq
UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269).
UG1433 (v1.2) October 27, 2021
RF Data Converter Evaluation Tool User Guide
Figure 2: High-level Hardware Architecture
RF_Analyzer
s00_0
s01_0
s02_0
s03_0
s10_0
s11_0
s12_0
s13_0
user_select_00_0
user_select_01_0
user_select_02_0
user_select_03_0
user_select_10_0
user_select_11_0
user_select_12_0
user_select_13_0
Chapter 3: Hardware Design
m00_0
m01_0
ADC_DDR_DMA
m02_0
m03_0
m10_0
m11_0
m12_0
m13_0
m20_0
m21_0
m22_0
m23_0
m30_0
m31_0
m32_0
m33_0
Send Feedback
S10_AXIS
S11_AXIS
S12_AXIS
S13_AXIS
S20_AXIS
S21_AXIS
S22_AXIS
S23_AXIS
S30_AXIS
S31_AXIS
S32_AXIS
S33_AXIS
S00_AXIS
S01_AXIS
S02_AXIS
S03_AXIS
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