Texas Instruments MSP430F663x Manual

Texas Instruments MSP430F663x Manual

Mixed signal microcontroller
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FEATURES
1
Low Supply Voltage Range: 1.8 V to 3.6 V
2
Ultralow Power Consumption
– Active Mode (AM):
All System Clocks Active:
270 µA/MHz at 8 MHz, 3.0 V, Flash Program
Execution (Typical)
– Standby Mode (LPM3):
Watchdog With Crystal, and Supply
Supervisor Operational, Full RAM
Retention, Fast Wake-Up:
1.8 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)
– Shutdown RTC Mode (LPM3.5):
Shutdown Mode, Active Real-Time Clock
With Crystal:
1.1 µA at 3.0 V (Typical)
– Shutdown Mode (LPM4.5):
0.3 µA at 3.0 V (Typical)
Wake-Up From Standby Mode in 3 µs (Typical)
16-Bit RISC Architecture, Extended Memory,
up to 20-MHz System Clock
Flexible Power Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring,
and Brownout
Unified Clock System
– FLL Control Loop for Frequency
Stabilization
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– Low-Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Crystals (XT1)
– High-Frequency Crystals Up to 32 MHz
(XT2)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MIXED SIGNAL MICROCONTROLLER
SLAS566C – JUNE 2010 – REVISED AUGUST 2012
Four 16-Bit Timer With 3, 5, or 7
Capture/Compare Registers
Two Universal Serial Communication
Interfaces
– USCI_A0 and USCI_A1 Each Support:
– Enhanced UART Supports Auto-
Baudrate Detection
– IrDA Encoder and Decoder
– Synchronous SPI
– USCI_B0 and USCI_B1 Each Support:
2
TM
– I
C
– Synchronous SPI
Full-Speed Universal Serial Bus (USB)
– Integrated USB-PHY
– Integrated 3.3-V and 1.8-V USB Power
System
– Integrated USB-PLL
– Eight Input and Eight Output Endpoints
12-Bit Analog-to-Digital (A/D) Converter With
Internal Shared Reference, Sample-and-Hold,
and Autoscan Feature
Dual 12-Bit Digital-to-Analog (D/A) Converters
With Synchronization
Voltage Comparator
Integrated LCD Driver With Contrast Control
for up to 160 Segments
Hardware Multiplier Supporting 32-Bit
Operations
Serial Onboard Programming, No External
Programming Voltage Needed
Six-Channel Internal DMA
Real-Time Clock Module With Supply Voltage
Backup Switch
Family Members are Summarized in
For Complete Module Descriptions, See the
MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208)
Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F663x
Table 1

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Summary of Contents for Texas Instruments MSP430F663x

  • Page 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
  • Page 2 DESCRIPTION The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
  • Page 3 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at http://www.ti.com/packaging. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 4 2 Timer_A Segments Timer_A Timer_B Reference Interface/ 5 CC each with 7 CC 1.5V, 2.0V, Battery 16 Channels 3 CC 2.5V Registers Registers Backup (12 ext/4 int) Port PJ Registers System Autoscan Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 5 6 Channel JTAG/ Comp_B MPY32 CRC16 Segments 2 Timer_A Reference Timer_A Timer_B Interface/ each with 5 CC 7 CC 1.5V, 2.0V, Battery 3 CC 2.5V Registers Registers Backup Port PJ Registers System Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 6 P8.3/UCA1RXD/UCA1SOMI/S12 P5.6/ADC12CLK/DMAE0 P8.2/UCA1TXD/UCA1SIMO/S13 P2.0/P2MAP0 P8.1/UCB1STE/UCA1CLK/S14 P2.1/P2MAP1 P8.0/TB0CLK/S15 P4.7/TB0OUTH/SVMOUT/S16 P2.2/P2MAP2 P2.3/P2MAP3 P4.6/TB0.6/S17 P2.4/P2MAP4 P4.5/TB0.5/S18 P2.5/P2MAP5 P4.4/TB0.4/S19 P2.6/P2MAP6/R03 P4.3/TB0.3/S20 P2.7/P2MAP7/LCDREF/R13 P4.2/TB0.2/S21 DVCC1 P4.1/TB0.1/S22 CAUTION: LCDCAP/R33 must be connected to DV if not used. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 7 P8.3/UCA1RXD/UCA1SOMI/S12 P5.6/ADC12CLK/DMAE0 P8.2/UCA1TXD/UCA1SIMO/S13 P2.0/P2MAP0 P8.1/UCB1STE/UCA1CLK/S14 P2.1/P2MAP1 P8.0/TB0CLK/S15 P4.7/TB0OUTH/SVMOUT/S16 P2.2/P2MAP2 P2.3/P2MAP3 P4.6/TB0.6/S17 P2.4/P2MAP4 P4.5/TB0.5/S18 P2.5/P2MAP5 P4.4/TB0.4/S19 P2.6/P2MAP6/R03 P4.3/TB0.3/S20 P2.7/P2MAP7/LCDREF/R13 P4.2/TB0.2/S21 DVCC1 P4.1/TB0.1/S22 CAUTION: LCDCAP/R33 must be connected to DV if not used. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 8 P8.3/UCA1RXD/UCA1SOMI/S12 P5.6/DMAE0 P8.2/UCA1TXD/UCA1SIMO/S13 P2.0/P2MAP0 P8.1/UCB1STE/UCA1CLK/S14 P2.1/P2MAP1 P8.0/TB0CLK/S15 P4.7/TB0OUTH/SVMOUT/S16 P2.2/P2MAP2 P2.3/P2MAP3 P4.6/TB0.6/S17 P2.4/P2MAP4 P4.5/TB0.5/S18 P2.5/P2MAP5 P4.4/TB0.4/S19 P2.6/P2MAP6/R03 P4.3/TB0.3/S20 P2.7/P2MAP7/LCDREF/R13 P4.2/TB0.2/S21 DVCC1 P4.1/TB0.1/S22 CAUTION: LCDCAP/R33 must be connected to DV if not used. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 9 SLAS566C – JUNE 2010 – REVISED AUGUST 2012 Pin Designation, MSP430F6638IZQW, MSP430F6637IZQW, MSP430F6636IZQW, MSP430F6635IZQW, MSP430F6634IZQW, MSP430F6633IZQW, MSP430F6632IZQW, MSP430F6631IZQW, MSP430F6630IZQW ZQW PACKAGE (TOP VIEW) NOTE: For terminal assignments, see Table 3 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 10 Input terminal for crystal oscillator XT1 XOUT Output terminal of crystal oscillator XT1 AVSS2 Analog ground supply (1) I = input, O = output, N/A = not available on this package offering Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 11 LCD common output COM3 for LCD backplane LCD segment output S40 (2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, C VCORE Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 12 P3.3/TA1.2/S28 Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output LCD segment output S28 General-purpose digital I/O with port interrupt Timer TA2 clock input P3.4/TA2CLK/SMCLK/S27 SMCLK output LCD segment output S27 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 13 General-purpose digital I/O P8.1/UCB1STE/UCA1CLK/S14 USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output LCD segment output S14 General-purpose digital I/O P8.2/UCA1TXD/UCA1SIMO/S13 USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out LCD segment output S13 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 14 General-purpose digital I/O - controlled by USB control register PU.1/DM USB data terminal DM VBUS USB LDO input (connect to USB power source) VUSB USB LDO output USB regulated power (internal use only, no external current loading) Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 15 Analog input A2 – ADC (not available on F6632, F6631, F6630 devices) General-purpose digital I/O P6.3/CB3/A3 Comparator_B input CB3 Analog input A3 – ADC (not available on F6632, F6631, F6630 devices) Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 16 MSP430F663x SLAS566C – JUNE 2010 – REVISED AUGUST 2012 www.ti.com Table 3. Terminal Functions (continued) TERMINAL DESCRIPTION NAME Reserved Reserved. It is recommended to connect to ground (DVSS, AVSS). Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 17: Short-Form Description

    M(R10) → M(Tab+R6) M(R10) → R11 Indirect auto-increment MOV @Rn+,Rm MOV @R10+,R11 R10 + 2 → R10 Immediate MOV #X,TONI MOV #45,TONI #45 → M(TONI) (1) S = source, D = destination Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 18: Operating Modes

    – Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4 • Low-power mode 4.5 (LPM4.5) – Internal regulator disabled – No data retention – Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 19: Interrupt Vector Addresses

    The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 6. Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations SYSTEM...
  • Page 20: Memory Organization

    MSP430F663x SLAS566C – JUNE 2010 – REVISED AUGUST 2012 www.ti.com Table 6. Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations (continued) SYSTEM WORD INTERRUPT SOURCE INTERRUPT FLAG PRIORITY INTERRUPT ADDRESS 0FFC8h Reserved Reserved ⋮ ⋮ 0FF80h 0, lowest (6) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatability with other devices, it is recommended to reserve these locations.
  • Page 21: Bootstrap Loader (Bsl)

    MSP430(tm) Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320). Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 22: Flash Memory

    The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during operation from a backup supply if the Battery Backup System module is implemented. There are 8 bytes of Backup RAM available on MSP430F663x. It can be wordwise accessed via the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.
  • Page 23 USCI_B0 clock input/output (direction controlled by USCI) PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI - input) PM_MCLK MCLK Reserved Reserved for test purposes. Do not use this setting. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 24 (Link to User's Guide) The clock system in the MSP430F663x family of devices is supported by the Unified Clock System (UCS) module that includes support for a 32-kHz watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not...
  • Page 25 019Eh SVMH_OVP (POR) DoPOR (POR) WDT timeout (PUC) WDT key violation (PUC) KEYV flash key violation (PUC) Reserved Peripheral area fetch (PUC) PMM key violation (PUC) Reserved 22h to 3Eh Lowest Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 26 NMIFG Highest OFIFG SYSUNIV, User NMI 019Ah ACCVIFG BUSIFG Reserved 0Ah to 1Eh Lowest No interrupt pending SYSBERRIV, Bus Error USB wait state timeout 0198h Highest Reserved 04h to 1Eh Lowest Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 27 DMA trigger event when selected. (2) Only on devices with peripheral module ADC12_A. Reserved on devices without ADC. (3) Only on devices with peripheral module DAC12_A. Reserved on devices without DAC. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 28 The USCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, or IrDA. The USCI_Bn module provides support for SPI (3 or 4 pin) or I2C. The MSP430F663x series includes two complete USCI modules (n = 0 to 1). Timer TA0 (Link to User's Guide) Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers.
  • Page 29 CCI1A 44-P3.2 M8-P3.2 DAC12_A CBOUT CCI1B DAC12_0, DAC12_1 (internal) CCR1 TA1.1 (internal) 45-P3.3 L8-P3.3 TA1.2 CCI2A 45-P3.3 L8-P3.3 ACLK CCI2B (internal) CCR2 TA1.2 (1) Only on devices with peripheral module DAC12_A. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 30 47-P3.5 M9-P3.5 TA2.0 CCI0A 47-P3.5 M9-P3.5 CCI0B CCR0 TA2.0 48-P3.6 L9-P3.6 TA2.1 CCI1A 48-P3.6 L9-P3.6 CBOUT CCI1B (internal) CCR1 TA2.1 49-P3.7 M10-P3.7 TA2.2 CCI2A 49-P3.7 M10-P3.7 ACLK CCI2B (internal) CCR2 TA2.2 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 31 TB0.6 CCI6B P2MAPx P2MAPx CCR6 TB0.6 (1) Timer functions selectable via the port mapping controller. (2) Only on devices with peripheral module ADC12_A. (3) Only on devices with peripheral module DAC12_A. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 32 Two hardware triggers or breakpoints on CPU register write access • Up to ten hardware triggers can be combined to form complex triggers or breakpoints • Two cycle counters • Sequencer • State storage • Clock control on module level Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 33 000h - 01Fh LCD_B control (see Table 0A00h 000h - 05Fh (1) For a detailed description of the individual control register offset addresses, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 34 UCS control 1 UCSCTL1 UCS control 2 UCSCTL2 UCS control 3 UCSCTL3 UCS control 4 UCSCTL4 UCS control 5 UCSCTL5 UCS control 6 UCSCTL6 UCS control 7 UCSCTL7 UCS control 8 UCSCTL8 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 35 Port P1 interrupt enable P1IE Port P1 interrupt flag P1IFG Port P2 input P2IN Port P2 output P2OUT Port P2 direction P2DIR Port P2 pullup/pulldown enable P2REN Port P2 drive strength P2DS Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 36 P5DS Port P5 selection P5SEL Port P6 input P6IN Port P6 output P6OUT Port P6 direction P6DIR Port P6 pullup/pulldown enable P6REN Port P6 drive strength P6DS Port P6 selection P6SEL Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 37 TA0 counter register TA0R Capture/compare register 0 TA0CCR0 Capture/compare register 1 TA0CCR1 Capture/compare register 2 TA0CCR2 Capture/compare register 3 TA0CCR3 Capture/compare register 4 TA0CCR4 TA0 expansion register 0 TA0EX0 TA0 interrupt vector TA0IV Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 38 Capture/compare control 1 TA2CCTL1 Capture/compare control 2 TA2CCTL2 TA2 counter register TA2R Capture/compare register 0 TA2CCR0 Capture/compare register 1 TA2CCR1 Capture/compare register 2 TA2CCR2 TA2 expansion register 0 TA2EX0 TA2 interrupt vector TA2IV Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 39 32-bit operand 1 – multiply low word MPY32L 32-bit operand 1 – multiply high word MPY32H 32-bit operand 1 – signed multiply low word MPYS32L 32-bit operand 1 – signed multiply high word MPYS32H Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 40 DMA Channel 3 destination address low DMA3DAL DMA Channel 3 destination address high DMA3DAH DMA Channel 3 transfer size DMA3SZ DMA Channel 4 control DMA4CTL DMA Channel 4 source address low DMA4SAL Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 41 USCI synchronous receive buffer UCB0RXBUF USCI synchronous transmit buffer UCB0TXBUF USCI I2C own address UCB0I2COA USCI I2C slave address UCB0I2CSA USCI interrupt enable UCB0IE USCI interrupt flags UCB0IFG USCI interrupt vector word UCB0IV Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 42 ADC12MCTL2 ADC memory-control register 3 ADC12MCTL3 ADC memory-control register 4 ADC12MCTL4 ADC memory-control register 5 ADC12MCTL5 ADC memory-control register 6 ADC12MCTL6 ADC memory-control register 7 ADC12MCTL7 ADC memory-control register 8 ADC12MCTL8 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 43 REGISTER OFFSET Comp_B control register 0 CBCTL0 Comp_B control register 1 CBCTL1 Comp_B control register 2 CBCTL2 Comp_B control register 3 CBCTL3 Comp_B interrupt register CBINT Comp_B interrupt vector word CBIV Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 44 LCD_B memory 1 LCDM1 020h LCD_B memory 2 LCDM2 021h ⋮ ⋮ ⋮ LCD_B memory 22 LCDM22 035h LCD_B blinking memory 1 LCDBM1 040h LCD_B blinking memory 2 LCDBM2 041h ⋮ ⋮ ⋮ Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 45: Register Description

    MSP430F663x www.ti.com SLAS566C – JUNE 2010 – REVISED AUGUST 2012 Table 54. LCD_B Registers (Base Address: 0A00h) (continued) REGISTER DESCRIPTION REGISTER OFFSET LCD_B blinking memory 22 LCDBM22 055h Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 46: Absolute Maximum Ratings

    (2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold parameters for the exact values and further details. (3) USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 47 1, 2, 3 0, 1 0, 1, 2 0, 1, 2, 3 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 1. Frequency vs Supply Voltage Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 48: Cc Excluding External Current

    (3) Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0). = 32786 Hz, f at specified frequency. ACLK MCLK SMCLK XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 49: Low-Power Mode Supply Currents

    SMCLK ACLK current drawn on VBAK (11) f = 0 MHz, f = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK MCLK SMCLK ACLK Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 50: Schmitt-Trigger Inputs - General Purpose I/O

    UNIT 1.8 V 0.80 1.40 Positive-going input threshold voltage 1.50 2.10 (1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN). Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 51: Inputs - Ports P1, P2, P3, And P4

    , for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop (OHmax) (OLmax) specified. (2) The maximum total current, I and I , for all outputs combined should not exceed ±100 mA to hold the maximum voltage (OHmax) (OLmax) drop specified. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 52: Outputs - General Purpose I/O (Reduced Drive Strength)

    The output is connected to the center tap of the divider. (3) The output voltage reaches at least 10% and 90% V at the specified toggle frequency. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 53: Typical Characteristics - Outputs, Reduced Drive Strength (Pxds.y = 0)

    T = 85°C −6.0 −20.0 T = 25°C T = 25°C −7.0 −8.0 −25.0 V – High-Level Output Voltage – V V – High-Level Output Voltage – V Figure 4. Figure 5. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 54: Typical Characteristics - Outputs, Full Drive Strength (Pxds.y = 1)

    T = 85°C −16 −50.0 −55.0 T = 25°C T = 25°C −20 −60.0 V – High-Level Output Voltage – V V – High-Level Output Voltage – V Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 55: Crystal Oscillator, Xt1, Low-Frequency Mode

    (7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. (8) Measured with logic-level input frequency but also applies to operation with crystals. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 56: Crystal Oscillator, Xt2

    (7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. (8) Measured with logic-level input frequency but also applies to operation with crystals. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 57: Internal Very-Low-Power Low-Frequency Oscillator (Vlo)

    (1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C)) (2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V) Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 58: Dco Frequency

    = 1 MHz, %/°C DCO frequency voltage drift = 1 MHz Typical DCO Frequency, V = 3.0 V, T = 25°C DCOx = 31 DCOx = 0 DCORSEL Figure 10. Typical DCO frequency Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 59: Pmm, Brown-Out Reset (Bor)

    VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 60: Pmm, Svm High Side

    TEST CONDITIONS UNIT SVMLE = 0, PMMCOREV = 2 current consumption SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 (SVML) SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 µA Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 61: Wake-Up From Low-Power Modes And Reset

    Timer_B input clock frequency External: TBCLK 1.8 V, 3 V Duty cycle = 50% ± 10% All capture inputs, Timer_B capture timing Minimum pulse duration required for 1.8 V, 3 V TB,cap capture Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 62: Battery Backup

    (1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 63: Usci (Spi Master Mode)

    SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 11 and . UCxCLK CKPL = 0 UCLK CKPL = 1 LO/HI LO/HI SU,MI HD,MI SOMI HD,MO VALID,MO SIMO Figure 11. SPI Master Mode, CKPH = 0 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 64 SLAS566C – JUNE 2010 – REVISED AUGUST 2012 www.ti.com UCxCLK CKPL = 0 UCLK CKPL = 1 LO/HI LO/HI HD,MI SU,MI SOMI HD,MO VALID,MO SIMO Figure 12. SPI Master Mode, CKPH = 1 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 65: Usci (Spi Slave Mode)

    (2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams Figure 13 Figure (3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 13 Figure Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 66 Figure 13. SPI Slave Mode, CKPH = 0 STE,LEAD STE,LAG UCxCLK CKPL = 0 UCLK CKPL = 1 LO/HI LO/HI HD,SI SU,SI SIMO HD,MO STE,ACC STE,DIS VALID,SO SOMI Figure 14. SPI Slave Mode, CKPH = 1 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 67 2.2 V, 3 V µs SU,STO > 100 kHz 2.2 V Pulse width of spikes suppressed by input filter HD,STA SU,STA HD,STA HIGH SU,DAT SU,STO HD,DAT Figure 15. I2C Mode Timing Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 68: Lcd_B, Recommended Operating Conditions

    LCD2B = 1 Analog input voltage at R03 R0EXT = 1 Voltage difference between V LCDCPEN = 0, R0EXT = 1 External LCD reference voltage applied VLCDREFx = 01 LCDREF/R13 at LCDREF/R13 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 69: Lcd_B, Electrical Characteristics

    (3) The internal reference supply current is not included in current consumption parameter I ADC12 (4) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 70 Differential linearity error 2.2 V, 3 V ±1 (1) Parameters are derived using the histogram method. (2) AVCC as reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 0. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 71 (3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t SENSOR(on) (4) The on-time t is included in the sampling time t ; no additional on time is needed. VMID(on) VMID(sample) Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 72: Ref, External Reference

    (5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 73: Ref, Built-In Reference

    ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). (7) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)). Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 74 (1) Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b" of the first-order equation: y = a + bx. V + (1 + E ) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1. DAC12_xOUT (2) This parameter is not production tested. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 75 DAC V DAC Output ¥ Load Ideal transfer function Offset Error Gain Error = 100 pF Load Positive Negative DAC Code Figure 17. Linearity Test Load Conditions and Gain/Offset Definition Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 76 (1) Data is valid after the offset calibration of the output amplifier. O/P(DAC12_x) Load Load DAC12 = 100 pF O/P(DAC12_x) Load AV – 0.3 V Figure 18. DAC12_x Output Resistance Tests Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 77 Conversion 2 Conversion 3 ±1/2 LSB DAC Output Glitch = 3 k Energy Load Load ±1/2 LSB = 100 pF Load O/P(DAC12.x) settleLH settleHL Figure 19. Settling Time and Glitch Energy Testing Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 78: Test Conditions

    Load DAC12_xDA T 080h 7F7h 080h 7F7h 080h DAC12_0 DAC0 = 100 pF Load REF+ DAC12_yOUT Load Load DAC12_xOUT DAC12_1 DAC1 oggle = 100 pF Load Figure 22. Crosstalk Test Conditions Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 79 VIN × VIN × VIN × Reference voltage for a given VIN = reference into resistor ladder, (n+0.5) (n+1) (n+1.5) CB_REF n = 0 to 31 / 32 / 32 / 32 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 80: Usb Output Ports Dp And Dm

    (3) A current overload is detected when the total current supplied from the USB LDO, including I , exceeds this value. USB_EXT (4) Does not include current contribution of Rpu and Rpd as outlined in the USB specification. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 81: Usb-Pll (Usb Phase-Locked Loop)

    (1) Tools that access the Spy-Bi-Wire interface must wait for the t time after pulling the TEST/SBWTCK pin high before applying the SBW,En first SBWTCK clock edge. (2) f may be restricted to meet the timing requirements of the module selected. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 82: Input/Output Schematics

    Module X OUT P1.0/TA0CLK/ACLK/S39 P1DS.x P1.1/TA0.0/S38 P1SEL.x 0: Low drive P1.2/TA0.1/S37 1: High drive P1.3/TA0.2/S36 P1.4/TA0.3/S35 P1IN.x P1.5/TA0.4/S34 P1.6/TA0.1/S33 P1.7/TA0.2/S32 Keeper Module X IN P1IE.x P1IRQ.x P1IFG.x P1SEL.x Interrupt Edge P1IES.x Select Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 83 I: 0; O: 1 Timer TA0.CCI1B capture input Timer TA0.1 output P1.7/TA0.2/S32 7 P1.7 (I/O) I: 0; O: 1 Timer TA0.CCI2B capture input Timer TA0.2 output (1) X = Don't care Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 84: Port P2, P2.0 To P2.7, Input/Output With Schmitt Trigger

    P2.0/P2MAP0 P2DS.x P2.1/P2MAP1 P2SEL.x 0: Low drive P2.2/P2MAP2 1: High drive P2.3/P2MAP3 P2.4/P2MAP4 P2IN.x P2.5/P2MAP5 P2.6/P2MAP6/R03 From Port Mapping P2.7/P2MAP7/LCDREF/R13 To Port Mapping P2IE.x P2IRQ.x P2IFG.x P2SEL.x Interrupt Edge P2IES.x Select Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 85 Mapped secondary digital function ≤ 19 = 31 P2.7/P2MAP7/ 7 P2.7 (I/O) I: 0; O: 1 LCDREF/R13 Mapped secondary digital function ≤ 19 LCDREF/R13 = 31 (1) X = Don't care Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 86: Port P3, P3.0 To P3.7, Input/Output With Schmitt Trigger

    Module X OUT P3.0/TA1CLK/CBOUT/S31 P3DS.x P3.1/TA1.0/S30 P3SEL.x 0: Low drive P3.2/TA1.1/S29 1: High drive P3.3/TA1.2/S28 P3.4/TA2CLK/SMCLK/S27 P3IN.x P3.5/TA2.0/S26 P3.6/TA2.1/S25 P3.7/TA2.2/S24 Keeper Module X IN P3IE.x P3IRQ.x P3IFG.x P3SEL.x Interrupt Edge P3IES.x Select Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 87 I: 0; O: 1 Timer TA2.CCI1A capture input Timer TA2.1 output P3.7/TA2.2/S24 7 P3.7 (I/O) I: 0; O: 1 Timer TA2.CCI2A capture input Timer TA2.2 output (1) X = Don't care Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 88: Port P4, P4.0 To P4.7, Input/Output With Schmitt Trigger

    Module X OUT P4.0/TB0.0/S23 P4DS.x P4.1/TB0.1/S22 P4SEL.x 0: Low drive P4.2/TB0.2/S21 1: High drive P4.3/TB0.3/S20 P4.4/TB0.4/S19 P4IN.x P4.5/TB0.5/S18 P4.6/TB0.6/S17 P4.7/TB0OUTH/SVMOUT/S16 Keeper Module X IN P4IE.x P4IRQ.x P4IFG.x P4SEL.x Interrupt Edge P4IES.x Select Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 89 P4.7/TB0OUTH/ 7 P4.7 (I/O) I: 0; O: 1 SVMOUT/S16 Timer TB0.TB0OUTH SVMOUT (1) X = Don't care (2) Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 90: Port P5, P5.0 And P5.1, Input/Output With Schmitt Trigger

    (6) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. The ADC12_A, VREF– reference is available at the pin. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 91: Port P5, P5.2 To P5.7, Input/Output With Schmitt Trigger

    5 P5.5 (I/O) I: 0; O: 1 COM3 P5.6/ADC12CLK/DMAE0 6 P5.6 (I/O) I: 0; O: 1 ADC12CLK DMAE0 P5.7/RTCCLK 7 P5.7 (I/O) I: 0; O: 1 RTCCLK (1) X = Don't care Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 92: Port P6, P6.0 To P6.7, Input/Output With Schmitt Trigger

    2 if DAC12AMPx>1 To Comparator_B From Comparator_B CBPD.x DAC12AMPx>0 DAC12OPS P6REN.x P6DIR.x P6OUT.x P6.0/CB0/A0 P6DS.x P6.1/CB1/A1 P6SEL.x 0: Low drive P6.2/CB2/A2 1: High drive P6.3/CB3/A3 P6.4/CB4/A4 P6IN.x P6.5/CB5/A5 P6.6/CB6/A6/DAC0 P6.7/CB7/A7/DAC1 Keeper Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 93 (2) Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. (3) The ADC12_A channel Ax is connected internally to AV if not selected via the respective INCHx bits. (4) X = Don't care Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 94: Port P7, P7.2, Input/Output With Schmitt Trigger

    SLAS566C – JUNE 2010 – REVISED AUGUST 2012 www.ti.com Port P7, P7.2, Input/Output With Schmitt Trigger Pad Logic To XT2 P7REN.2 P7DIR.2 P7OUT.2 P7.2/XT2IN P7DS.2 P7SEL.2 0: Low drive 1: High drive P7IN.2 Keeper Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 95: Port P7, P7.3, Input/Output With Schmitt Trigger

    (2) Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal mode or bypass mode. (3) Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as general-purpose I/O. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 96: Port P7, P7.4 To P7.7, Input/Output With Schmitt Trigger

    2 if DAC12AMPx>1 To ADC12 INCHx = y To Comparator_B From Comparator_B CBPD.x DAC12AMPx>0 DAC12OPS P7REN.x P7DIR.x P7.4/CB8/A12 P7DS.x P7.5/CB9/A13 P7SEL.x 0: Low drive P7.6/CB10/A14/DAC0 1: High drive P7.7/CB11/A15/DAC1 P7IN.x Keeper Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 97 (2) Setting the P7SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. (3) The ADC12_A channel Ax is connected internally to AV if not selected via the respective INCHx bits. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 98: Port P8, P8.0 To P8.7, Input/Output With Schmitt Trigger

    0: Input From module 1: Output P8OUT.x Module X OUT P8.0/TB0CLK/S15 P8DS.x P8.1/UCB1STE/UCA1CLK/S14 P8SEL.x 0: Low drive P8.2/UCA1TXD/UCA1SIMO/S13 1: High drive P8.3/UCA1RXD/UCA1SOMI/S12 P8.4/UCB1CLK/UCA1STE/S11 P8IN.x P8.5/UCB1SIMO//UCB1SDA/S10 P8.6/UCB1SOMI/UCB1SCL/S9 P8.7/S8 Keeper Module X IN Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 99 P8.5/UCB1SIMO/UCB1SDA/S10 5 P8.5 (I/O) I: 0; O: 1 UCB1SIMO/UCB1SDA P8.6/UCB1SOMI/UCB1SCL/S9 6 P8.6 (I/O) I: 0; O: 1 UCB1SOMI/UCB1SCL P8.7/S8 7 P8.7 (I/O) I: 0; O: 1 (1) X = Don't care Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 100: Port P9, P9.0 To P9.7, Input/Output With Schmitt Trigger

    P9.4 (I/O) I: 0; O: 1 P9.5/S2 P9.5 (I/O) I: 0; O: 1 P9.6/S1 P9.6 (I/O) I: 0; O: 1 P9.7/S0 P9.7 (I/O) I: 0; O: 1 (1) X = Don't care Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 101 Hi-Z Outputs off Outputs enabled Outputs enabled Outputs enabled Outputs enabled Direction set by USB module Table 67. Port PUR Input Functions CONTROL BITS FUNCTION PUSEL PUREN Input disabled Pullup disabled Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 102 SLAS566C – JUNE 2010 – REVISED AUGUST 2012 www.ti.com Table 67. Port PUR Input Functions (continued) CONTROL BITS FUNCTION PUSEL PUREN Input disabled Pullup enabled Input enabled Pullup disabled Input enabled Pullup enabled Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 103 Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.x PJDIR.x DVSS PJOUT.x From JTAG PJ.1/TDI/TCLK PJDS.x PJ.2/TMS From JTAG 0: Low drive PJ.3/TCK 1: High drive PJIN.x To JTAG Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 104 (1) X = Don't care (2) Default condition (3) The pin direction is controlled by the JTAG module. (4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 105: Device Descriptors

    MSP430F663x www.ti.com SLAS566C – JUNE 2010 – REVISED AUGUST 2012 DEVICE DESCRIPTORS Table 69 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 69. MSP430F663x Device Descriptor Table F6638 F6637 F6636 F6635 F6634...
  • Page 106: Revision History

    Changed note (2) in 12-Bit ADC, Temperature Sensor and Built-In VMID. Editorial changes throughout. SLAS566D Changed description of the number of I/Os in each port in Digital I/O (Link to User's Guide). Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated...
  • Page 107: Packaging Information

    PACKAGE OPTION ADDENDUM www.ti.com 4-Apr-2013 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples Drawing MSP430F6630IPZ ACTIVE LQFP Green (RoHS CU NIPDAU Level-3-260C-168 HR M430F6630 & no Sb/Br) MSP430F6630IPZR ACTIVE LQFP...
  • Page 108 PACKAGE OPTION ADDENDUM www.ti.com 4-Apr-2013 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples Drawing MSP430F6633IZQWR ACTIVE 2500 Green (RoHS SNAGCU Level-3-260C-168 HR M430F6633 MICROSTAR & no Sb/Br) JUNIOR MSP430F6633ZQWT ACTIVE...
  • Page 109 PACKAGE OPTION ADDENDUM www.ti.com 4-Apr-2013 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples Drawing MSP430F6637IPZ ACTIVE LQFP Green (RoHS CU NIPDAU Level-3-260C-168 HR M430F6637 & no Sb/Br) MSP430F6637IPZR ACTIVE LQFP...
  • Page 110 PACKAGE OPTION ADDENDUM www.ti.com 4-Apr-2013 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) MSL, Peak Temp.
  • Page 111: Tape And Reel Information

    PACKAGE MATERIALS INFORMATION www.ti.com 29-Dec-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) MSP430F6632IPZR LQFP 1000 330.0 24.4 17.0 17.0 20.0 24.0 MSP430F6633IPZR...
  • Page 112 PACKAGE MATERIALS INFORMATION www.ti.com 29-Dec-2012 Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) MSP430F6638IPZR LQFP 1000 330.0 24.4 17.0 17.0 20.0 24.0 MSP430F6638IZQWR BGA MI 2500 330.0 16.4 12.0 16.0 CROSTA...
  • Page 113 PACKAGE MATERIALS INFORMATION www.ti.com 29-Dec-2012 Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) MSP430F6636IZQWR BGA MICROSTAR 2500 336.6 336.6 28.6 JUNIOR MSP430F6637IZQWT BGA MICROSTAR 336.6 336.6 28.6 JUNIOR MSP430F6638IPZR LQFP 1000 367.0 367.0 45.0 MSP430F6638IZQWR BGA MICROSTAR 2500 336.6 336.6...
  • Page 115: Mechanical Data

    MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 0,17 0,13 NOM 12,00 TYP Gage Plane 14,20 13,80 0,25 16,20 0,05 MIN 0 – 7 15,80 1,45 0,75 1,35 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96...
  • Page 116: Important Notice

    IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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