Denon AVR-S510BT Service Manual page 84

ADV7623 Hardware Manual
Location Mnemonic
49 TXGND
50 TX0-
51 TX0+
52 TXGND
53 TX1-
54 TX1+
55 TXAVDD
56 TX2-
57 TX2+
58 TXGND
59 CEC
60 DGND
61 DVDD
62 ALSB
63 CSB
64 EP_SCK
65 EP_CS
66 EP_MOSI
67 EP_MISO
Rev. 0 – March 2010
Type
Ground TXAVDD Ground
HDMI Output Differential Output Channel 0
Complement. Differential output of the red
data at 10× the pixel clock rate; supports
TMDS logic level.
HDMI Output Differential Output Channel 0 True.
Differential output of the red data at 10×
the pixel clock rate; supports TMDS logic
level.
Ground TXAVDD Ground
HDMI Output Differential Output Channel 1
Complement. Differential output of the red
data at 10× the pixel clock rate; supports
TMDS logic level.
HDMI Output Differential Output Channel 1 True.
Differential output of the red data at 10×
the pixel clock rate; supports TMDS logic
level.
Power 1.8V power supply for TMDS outputs
HDMI Output Differential Output Channel 2
Complement. Differential output of the red
data at 10× the pixel clock rate; supports
TMDS logic level.
HDMI Output Differential Output Channel 2 True.
Differential output of the red data at 10×
the pixel clock rate; supports TMDS logic
level.
Ground TXAVDD Ground
Digital I/O Consumer electronic control channel.
Ground Ground for DVDD
Power Digital supply voltage (1.8 V)
Digital Input This pin is used to set I2C address of the Rx
IO and the Tx Main Map.
Digital Input Chip Select pin. This pin must be set low or
left floating for the chip to process I2C
messages that are destined to the
ADV7623. The ADV7623 ignores I2C
messages which he receives if this pin is
high.
Digital Output SPI clock interface for the EDID/OSD
Digital Output SPI chip selected interface for the
EDID/OSD
Digital Output SPI master out/slave in for the EDID/OSD
Digital Input SPI master in/slave out for the EDID/OSD
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Description
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