Denon AVR-S510BT Service Manual page 103

TOP268VG (SMPS : IC601)
CONTROL (C)
Z
C
SHUNT REGULATOR/
ERROR AMPLIFIER
I
FB
EXTERNAL CURRENT
LIMIT (X)
VOLTAGE
MONITOR (V)
FREQUENCY (F)
Figure 3. Functional Block Diagram.
Pin Functional Description
DRAIN (D) Pin:
High-voltage power MOSFET DRAIN pin. The internal start-up
bias current is drawn from this pin through a switched high-
voltage current source. Internal current limit sense point for
drain current.
CONTROL (C) Pin:
Error amplifier and feedback current input pin for duty cycle
control. Internal shunt regulator connection to provide internal
bias current during normal operation. It is also used as the
connection point for the supply bypass and auto-restart/
compensation capacitor.
EXTERNAL CURRENT LIMIT (X) Pin:
Input pin for external current limit adjustment remote-ON/OFF
and device reset. A connection to SOURCE pin disables all
functions on this pin. This pin should not be left floating.
VOLTAGE MONITOR (V) Pin:
Input for OV, UV, line feed-forward with DC
overvoltage protection (OVP), remote-ON/OFF. A connection to
the SOURCE pin disables all functions on this pin. This pin should
not be left floating.
FREQUENCY (F) Pin :
Input pin for selecting switching frequency 132 kHz if connected
to SOURCE pin and 66 kHz if connected to CONTROL pin. This
pin should not be left floating.
SOURCE (S) Pin:
Output MOSFET source connection for high-voltage power return.
Primary-side control circuit common and reference point.
V
C
+
5.8 V
-
4.8 V
-
INTERNAL UV
5.8 V
+
COMPARATOR
V I (LIMIT)
CURRENT
LIMIT
ADJUST
ON/OFF
V + V
BG T
STOP LOGIC
1 V
V OVP OV/
UV
STOP SOFT
LINE
DC START
DC
SENSE MAX
MAX
OSCILLATOR
WITH JITTER
66k/132k
F REDUCTION
F REDUCTION
SOFT START
I
PWM
FB
K
I
PS(UPPER)
PS(UPPER)
K I
PS(LOWER) PS(LOWER)
reduction, output
MAX
0
INTERNAL
SUPPLY
1
SOFT START
÷ 16
SHUTDOWN/
AUTO-RESTART
HYSTERETIC
THERMAL
SHUTDOWN
D
MAX
CLOCK
S Q
R
OFF
NO CONNECTION (NC) Pin:
Internally not connected, floating potential pin.
Exposed Pad (On Bottom)
Internally Connected to
SOURCE Pin
Figure 4. Pin Configuration (Top View).
103
DRAIN (D)
-
+
K
-
PS(UPPER)
+
K
-
PS(LOWER)
+
CURRENT LIMIT
COMPARATOR
SOURCE (S)
CONTROLLED
TURN-ON
GATE DRIVER
LEADING
EDGE
BLANKING
PI-4511-012810 SOURCE (S)
K Package
(eSOP-12B)
V 1 12 S
X 2 11 S
C 3 10 S
F 4 9 S
8 S
D 6 7 S
PI-5568-061011
3