Denon AVR-S510BT Service Manual page 83

ADV7623 Hardware Manual
Location Mnemonic
27 RXD_0+
28 CGND
29 RXD_1-
30 RXD_1+
31 TVDD
32 RXD_2-
33 RXD_2+
34 CVDD
35 CGND
36 TXPVDD
37 TXPLVDD
38 TXGND
39 TXPGND
40 EXT_SWING
41 HPD_ARC-
42 ARC+
43 TXDDC_SDA
44 TXDDC_SCL
45 TXAVDD
46 TXGND
47 TXC-
48 TXC+
Rev. 0 – March 2010
Type
D in the HDMI interface.
HDMI Input Digital input channel 0 True of port D in
the HDMI interface.
Ground TVDD and CVDD Ground
HDMI Input Digital input channel 1 complement of port
D in the HDMI interface.
HDMI Input Digital input channel 1 true of port D in the
HDMI interface.
Power Receiver terminator supply voltage (3.3 V)
HDMI Input Digital input channel 2 complement of port
D in the HDMI interface.
HDMI Input Digital input channel 2 true of port D in the
HDMI interface.
Power Receiver comparator supply voltage (1.8V)
Ground TVDD and CVDD Ground
Power 1.8 V Power Supply for Digital and I/O
Power Supply. These pins supply power to
the digital logic and I/Os. They should be
filtered and as quiet as possible.
Power 1.8 V Power Supply.
Ground TXPVDD Ground
Ground TXPLVDD Ground
Analog Input Sets Internal Reference Currents. Place 887
Ω resistor (1% tolerance) between this pin
and ground.
Analog Input Hot Plug Detect Signal. This indicates to
the interface whether the receiver is
connected. Supports 1.8 V to 5.0V CMOS
logic levels.
Analog Input Audio return channel input
Digital I/O Serial Port Data I/O to Receiver. This pin
serves as the master to the DDC bus.
Supports a 5 V CMOS logic level.
Digital Input Serial Port Data Clock to Receiver. This pin
serves as the master clock for the DDC bus.
Supports a 5 V CMOS logic level.
Power 1.8V power supply for TMDS outputs
Ground TXAVDD Ground
HDMI Output Differential Clock Output. Differential
clock output at the TMDS clock rate;
supports TMDS logic level.
HDMI Output Differential Clock Output. Differential
clock output at the TMDS clock rate;
supports TMDS logic level.
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Description
Confidential NDA required