HP Vectra XU5 Reference Manual page 21

Instruction and Data Cache
The Pentium processor has separate code and data caches on-chip. Each cache is 8 KB in
size with a 32-bit line. The caches act as temporary storage for data and instructions from
the main memory. As the system is likely to use the same data several times, it is faster to
get it from the on-chip cache than from the main memory.
Each cache has a dedicated Translation Lookaside Buffer (TLB). The TLB is a cache of the
most recently accessed memory pages.The data cache is configured to be Write-Back on a
line-by-line basis(a line is an area of memory of a fixed size).
The data cache tags (directory entries used to reference cached memory pages) are triple
ported to support two data transfers and an inquire cycle in the same clock cycle.
The code cache tags are also triple ported to support snooping (a way of checking for
accesses to main memory by other devices) and split line accesses.
Individual pages of memory can be configured as cacheable or non-cacheable by software
or hardware, they can also be enabled and disabled by software or hardware.
Vectra XU Technical Reference System Overview 21