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The ADC device is programmable through the serial programming interface (SPI) bus accessible through
the FTDI USB-to-SPI converter located on the EVM. A GUI is provided to write instructions on the bus and
program the registers of the ADC device.
4.1
Supported JESD204C Device Features
The ADC device supports some configuration of the JESD204C interface. Due to limitations in the
TSW14J58EVM firmware, all JESD204C link features of the ADC device are not supported.
the supported and non-supported features.
Table 4-1. Supported and Non-Supported Features of the JESD204C Device
JESD204C Feature
Number of lanes per link (L)
Total number of lanes active
Number of frames per multiframe (K)
Scrambling
Encoding
Test patterns
Speed
(1)
Dependent on bypass or decimation mode and output rate selection. Always disable the JESD204 block before changing any of
the JESD204C settings. Once the settings are changed, re-enable the JESD204 block.
4.2
Tab Organization
Control of the ADC1 and ADC2 device features are available in the EVM, ADC PLL, Control and
JESD204C tabs for respective ADCs.
SLAU796 – July 2020
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Supported by ADC Device
(1)
L = 2, 3, 4, 6, 8
2,,3 4, 6, 8
(1)
K
= 4–256,
min
K
= 256, K
= 4, 16 or 32
max
step
Supported
8B/10B and 64B/66B
PRBS7, PRBS9, PRBS15, PBRS23, PRBS31, Ramp,
Transport Layer test, D21.5, K28.5, Repeat ILA,
Modified RPAT, Serial Out 0, Serial Out 1, Clock test,
(1)
ADC Test Pattern
Lane rates from 0.8 to 17.16 Gbps
Copyright © 2020, Texas Instruments Incorporated
Device Configuration
Supported by TSW14J58EVM
L = 1, 2, 3, 4, 6, 8 supported
2, 4, 6, 8, 12, 16
Most values of K supported, constrained by
requirement that
K × F = 4
Supported
ILA, Ramp, Long/Short Transport
Lane rates from 12 to 16 Gbps
(1)
ƒ
parameter must be properly set in HSDC
(SAMPLE)
Pro GUI.
Device Configuration
Chapter 4
SLAU796 – July 2020
Table 4-1
lists
n
8B/10B
15
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