Port Tests; Figure 7-4. Port Loopback Tests - ADTRAN 1203060L1 User Manual

Chapter 7 Test Menu
The self-test includes the following board-level tests, in this order:
1. RAM tests; EPROM checksum
2. On-board data path; sending a known test pattern through an on-board loop
3. Front panel LED verification
4. Phase lock loop verification. If a failure is detected, note the failure number and contact ADTRAN
Technical Support.
Executing self-test disrupts normal data flow and prevents remote communication until the
self-test is completed (approximately five seconds).

PORT TESTS

These two tests (
DTE L
loopback (see Figure 7-4). The
DTE. The
D L
ATA OOPBACK
52
and
D L
OOPBCK ATA OOPBCK
loops data received at the V.35 interface back towards the
DTE L
OOPBK
test the data is looped back just before going out the V.35 interface.
(NI)

Figure 7-4. Port Loopback Tests

© 2003 ADTRAN, Inc.
) control the activation of a DTE loopback and a data
TSU LT User Manual
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